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Duc D. Status: Offline
Hanoi, Vietnam
60% Job Success

FPGA and Embedded Linux System Engineer

10 YEAR EXPERIENCE IN FPGA and software design - 100% JOB COMPLETED - COMPLETED ABOVE 100 JOBS IN FPGA/VHDL/VERILOG - 200 VERY GOOD REVIEWS in freelancer.com I am an electronics engineer with excellent academic background, firm language skills (IELTS 6.0) and 10-years experience in TOP SKILLS below (Graduated Very Good Degree - Top 5% graduated Student at Top University in Vietnam) TOP SKILLS 1. FPGA Design. (VHDL/Verilog) 2. Embedded System Design. (Schematic, PCB Design) 3. Software Design. (C/C++ in Linux system) TOP PROJECTS - Ethereum Miner This is the big project which brought 400k USD profit for company and brings the 10M USD revenue for Xilinx. We released the first Ethereum miner for FPGA in the world and in the top in speed in 1 year. I worked in both software (C++ code) controller code and FPGA code. This FPGA code is driven at 600 MHz. In this project, I got the experience to drive high speed with HBM, how to overspeed the memory compared to the datasheet speed. - Other coin Miner (Handshake coin, Bitcore coin, Tellor coin…) Quite same as Ethereum Miner, those project are creating the miner for some small coins, but the difference is, while ethereum miner is the first memory hard algorithm implementation in the world, those coin is only computing coin. I drived in handshake project with 700Mhz in vu35p Xilinx chip, and has the triggier to track the temperature of the chip. - Database Server Emulation Creating the 100G Ethernet TCP/IP controller for the board Create the database string processing Create the memory controller This project might reduce the cost for the current database server and also reduce the latency to response to users. - Zynq and CPU DRAM Controller This is the project to make the switch between CPU and FPGA to control a DIMM to reduce the latency transfer data between CPU and FPGA. - Walker Recognition Design Human Detection IP on FPGA Zedboard using Verilog language. Design Camera Controller IP to capture images from Camera OV5640 storing into DDR3 RAM. I need to use XDMA xilinx ip core to transfer data between PL and PS. TOP SKILLS: • 100G TCP/IP in C1100 board • Improve timing and clock speed for a FPGA (My fastest design is 700MHz) • Partial Reconfiguration • Pcie XDMA Xilinx IP Core • Zynq Vitis, SDK and Controller, transfer data between PS and PL through DMA • Zynq Petalinux • Linux command skill • Familiar with Makefiles and Linux environment with command and tcl design • Familiar with cocotb, C++ cosimulation in Xcelium tools LANGUAGES -English: IELTS 6.0 (Reading 6.5, Speaking 6.5, Writing 6.0, Listening 5.5)
Work history
Skills

Skills

  • MetaTrader
  • VHDL
  • FPGA

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