Ankita T.
Hardoi, India
RTL design engineer, microarchitecture design
$15.00/hr
I am a RTL design engineer with 7+ years experience in verilog designing and 3+ years experience in RTL to gds ii designing.
Work history
Work history
Static Timing Analysis complete VIDEOCOURSE
Nov 20, 2023
-
May 23, 2024
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