We are pushing RTL through the backend tool flow, in order to generate a hard macro of our high performance, low power processor core. We need people on synthesis, PnR, extraction, and signoff (DRC, EM, ESD, antenna, LVS, and timing). Experience with CTS, power grid, scan chain, clock gating, ECOs, manual layout fixes, and so on would be helpful. Experience with all is not necessary :-)
Looking for experience on Synopsys, Cadence, or Mentor.
·Aspects of Physical Design include Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic). Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), and tapeout.
·Drive to signoff closure for tapeout
Less than 30 hrs/week
More than 3 months3+ monthsProject LengthDuration
I am looking for freelancers with the lowest rates