Overview
We are providing services in: - Functional Verification of ASIC/FPGA/SOC in SV/UVM. - Reusable SV/UVM verification components and VIP development. - Automate simulation flow through scripts Makefile, Python, Perl. - Complex DSP Math Library Algorithm implementation. - Functional and Code Coverage Analysis and Closure. - Regression Management, Debugging Simulation Failures and Regression Cleanup. - UVM Register Model Implementation. - Verification Architecture Development. - Implementation SV/UVM testbench component from scratch .
Upwork activity
Hourly rate
$40.00
Total earned
$20K
Total jobs
3
Member since