Design a schematics diagram for Altera MAX V CPLD 5M40ZE64 CPLD, which will be used to produce a evaluation/development board for this device.
-- Route as many IO pins as possible and provide descriptive names and port numbering for them.
-- Route the ISP pins and group them to a pin header compatible with Altera programmers.
-- Route and name the power input pins.
-- Add all the required active and passive components to ensure stable operation of the device.
-- Provide a file with a description for each pin, mentioning its number in EQFP package, all its configurable functions, input/output voltage and current limitations, etc.
-- Include a short textual overview of the board into the text file.
Assume that power is provided externally to the board.
The expected result should contain:
-- circuit drawing in PDF, SVG or another graphic format;
-- circuit definition file for one of the popular schematic editors;
-- a text file with pin description and board overview