Need to design a high speed counting circuit to detect the time difference between two separate signal pulses with 1nsec resolution. The leading edge of signal 1 pulse should start the count cycle, and the leading edge of signal 2 pulse should terminate the count cycle.
Please advise on most appropriate design. I have been envisioning synchronous counters clocked at 1 Ghz with a total of 32 bits, which could pass data through shift register(s) for transfer of data to unknown interface (possibly FPGA). Counting cycle could be enabled with signal from a latching comparator, and disabled by the signal of an additional comparator. Once the count is collected, the cycle is reset for the next set of pulses.
I have data sheets of circuit components that may work but am uncertain if they are the most appropriate selections. Deliverable includes selection and refinement of circuit components with associated BOM, generated circuit schematics, and associated PCB layout files.
Phase 1 - Select...