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Verilog Jobs

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Fixed-Price - Intermediate ($$) - Est. Budget: $49 - Posted
I need to send data from Matlab to the FPGA and output this data to a pin, in order to see the data in a oscilloscope. The code must be written in Verilog. The aim is to write a Verilog module to make a link between the UART and 2 RAMs (created using Core Generator, type of RAM is "Simple Dual Port RAM"), one for the incoming data and the other one for the outcoming data.
Skills: Verilog / VHDL Field-Programmable Gate Array (FPGA) MATLAB
Fixed-Price - Expert ($$$) - Est. Budget: $10,000 - Posted
Today I have a video processing system that ingests video from a SONY FCB-EH6500 Color HD Block Camera. The camera I need to ingest video from now is a Hitachi DI-SC120R Color HD CCD camera. I cannot make modifications to my current video processing system. Designing a new small PCB and schematic that converts the Hitachi video signal to look identical to the Sony. I will want the gerber files and full BOM as the end deliverable.
Skills: Verilog / VHDL Field-Programmable Gate Array (FPGA) PCB Design
Fixed-Price - Expert ($$$) - Est. Budget: $3,000 - Posted
I need a microcontroller / CPLD based linescan CCD camera system. The camera will interface to a PC via ethernet. I also need a test utility and a sdk to interface the hardware with my application software. 1. Need a linescan CCD camera designed for TCD104DG and ILX554B. 2. The controller should be able to read data from 3-4 CCDs operating at minimum integration time of 3ms (for tcd1304DG). 3. The controller should be interfaced to a PC by ethernet. 4. A test utility needs to be designed in C# 5. A dll/sdk needs to be provided to interface the end user application 6. Project involves following sub tasks. a. Component selection b. Schematic design c. PCB layout, PCB fabrication, component procurement d. firmware development e. sample interface software in C# f. A test utility to test the operation of the hardware in C#
  • Number of freelancers needed: 2
Skills: Verilog / VHDL C# Circuit Design Electronics
Hourly - Intermediate ($$) - Est. Time: 3 to 6 months, Less than 10 hrs/week - Posted
 Hands on knowledge in FPGA synthesis, implementation, and timing closure.  At least 3 years of experience in Verilog-based FPGA design.  At least 3 years of experience in Altera development environments
Skills: Verilog / VHDL
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