We have designed a high speed low power CPU for Big Data acceleration, and are looking for people to be part of implementing a prototype of it.
The project is based on the RISC-V instruction set from UC Berkeley, and will use the Rocket Chip as a starting point. That is actually implemented in a tool called Chisel that UC Berkeley created, so part of this job will be learning the Chisel tool. Chisel generates a behavioral model. That's what we need -- we need that behavioral model, as fast as possible.
There is one person already working on this project, who has gotten the Berkeley tools up and running, has compiled the Rocket Chip to verilog, and then compiled the verilog to FPGA, and has generated a behavioral model of Rocket Chip.
You will work together with them, to start modifying the internals of Rocket Chip. We will reuse as much code as is reasonable. But, your work will be to rip up the Rocket core and replace it with the new, novel micro-architecture.
(The new uArchitecture is able to deliver the same speed as a Xeon, at 3.5GHz, while delivering higher instructions per cycle on data intensive workloads, at 1.9 IPC, but at very low power -- about 40mW -- and very small area -- about 0.1mm^2)