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Hourly - Intermediate ($$) - Est. Time: Less than 1 month, Less than 10 hrs/week - Posted
Looking for someone to help make the following mods to https://github.com/drxzcl/neppielight: 1. use WS2811/WS2812 instead of WS2801 2. replace accumulator/averaging logic with one on-chip FIFO per HDMI display column 3. add option to use alternating even/odd frames and refresh at 30 FPS Overview: The purpose of the project is to use a Xilinx Spartan 6 FPGA to drive at least 32 strings of WS2811/WS2812 smart LEDs from an HDMI signal. ... I'm working my way up the CPLD and FPGA learning curve, but it's taking me more time than I currently have available. Restrictions/environment: - target device is a Xilinx Spartan 6 XC6SLX9-2C TQG144, 100 MHz clock (Numato Mimas board, no off-chip SDRAM); the Scarab miniSpartan 6+ seems to be no longer available and Neppielight did not require external RAM so I'd like to use the Numato Mimas, but I am open to using other inexpensive alternatives - must be able to build the synthesized code with a recent ISE WebPack (free license), for example, 14.7; no use of high-end licensed tools or proprietary IP (target audience is hobbyists) - needs to handle at least XGA (1024 x 768) HDMI signal, no DMCA (ie, encryption) since the source is a computer display adapter - needs to provide at least 32 display columns, or the maximum number within the available on-chip RAM - TDMS re-encoding (output) can be dropped if needed, but is preferable to leave that intact in order to make usage and testing easier - use any computer as the HDMI signal source (non-encrypted); I'm using a laptop or a Raspberry Pi 2, but that should not matter as long as it is low enough video rate - Verilog preferred, but VHDL is acceptable (I realize neppielight is in VHDL) - FPGA output timing should be compatible with both WS2811 and WS2812 (running in "fast" mode at 800 KHz); from other projects I know the same timing can be used with both - WS2811/WS2812 outputs from the FPGA should be inverted (compile-time option); this will make it easier to use with simple transistor level shifters - project should use a compile-time Parameter for FPGA clock speed (100 MHz currently) Project milestones: 1. ... WS281X output (attached) - LED datasheets (for timing info): WS2801 datasheet: https://cdn-shop.adafruit.com/datasheets/WS2801.pdf WS2811 datasheet: https://cdn-shop.adafruit.com/datasheets/WS2811.pdf WS2812 datasheet: https://cdn-shop.adafruit.com/datasheets/WS2812.pdf - XGA timing: http://tinyvga.com/vga-timing/1024x768@60Hz - Neppielight info: http://zerocharactersleft.blogspot.nl/2015/04/diy-fpga-based-hdmi-ambient-lighting.html - Neppielight source code: https://github.com/drxzcl/neppielight - FPGA board references: http://numato.com/mimas-spartan-6-fpga-development-board/ http://www.scarabhardware.com/minispartan6/ - Xilinx app note on HDMI/TDMS: http://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf Any other reference material needed?
Skills: Xilinx Field-Programmable Gate Array (FPGA) Verilog / VHDL
Fixed-Price - Expert ($$$) - Est. Budget: $100 - Posted
I need an expert in Computer engineering major. who can help me in these coerces. Discrete Structures with Computing Applications & Principles of Computer Engineering & Computer Logic Design: (Sequential logic emphasizing Finite State Machine design & analysis, timing analysis of sequential logic, Introduction to Data Path, Control and Memory. Use of Electronic Design Automation (EDA) tools for design, simulation, verification. Laboratory projects with Field Programmable Gate Arrays (FPGA’s). )
Skills: Xilinx Computer Engineering Mathematics Verilog / VHDL
Hourly - Expert ($$$) - Est. Time: More than 6 months, 30+ hrs/week - Posted
We are currently looking for a XILINX ZYNQ specialists who has worked with Video / image processing. We want one video / image processing specialist who is very experienced in Zynq + mandatory skill set : 1- VIVADO 2- AXI 3- VHDL 4- video and image processing-related experience in architecture, design, writing ip cores, and integration to a Zynq-based system Apply only if you have extensive experience with ZYNQ and VIVADO.
Skills: Xilinx ARM Field-Programmable Gate Array (FPGA) Image Processing