I am a student with a major in Electronics. Recently, I have finished a project on FPGA and would like to deepen my knowledge with some additional tutoring. This project was done in VHDL on Vivado Software. It is simulated on a behavioral part and is also synthesizable. I am interested in:
- reports reading (especially timing reports)
- further design optimization (How to determine what part of the design consumes the most resources?)
- constrains considerations and implementation
- DRC reading
- of course some tips on VHDL
- getting rid of super annoying warnings (I know it's not always possible, but..)
- ChipScope usage.
All based on the Vivado software, since it’s so damn confusing. My hardware part is Nexys 4 DDR Board, which has Artix 7 FPGA.
Basically, I would like to take some lessons on Skype. We can take my project, synthesize it and go through various steps and I will ask you 1001 questions :). The lessons can be held in English, Russian or German, I am fluent in all of them.