Fpga Jobs

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Fixed-Price - Intermediate ($$) - Est. Budget: $10 - Posted
We would like to use wide band SDR such as bladeRF or other, in order to implement 20 receivers in the 2.4Ghz band. Receivers should be 1 or 2 mbps, gfsk, with predefined properties. Simple version should detect RSSI over noise (and maybe preamble) and send I/Q samples together with time stamp. A better version will run bit synchroniser on each channel and only send bits if rssi above threshold. budget and time line to be agreed.
Skills: Field-Programmable Gate Array (FPGA) Digital Signal Processing
Fixed-Price - Intermediate ($$) - Est. Budget: $300 - Posted
Need to have circuit designs implemented into 84 pin Atmega 1508AS CPLD design. I would supply the circuits thats need to be implemented into the gate array and an image of the pinout assignments of where the circuit connections map to. This work was previously done on a 64 pin 1504AS in VHDL, however the coder didn't supply the source JEDEC files in PLD format but rather VHDL and we are unable to use those files to modify and transfer the code to the larger 1508AS. Coder has since stopped communicating and we now paid for a code which we can't use in a larger array chip. Would need the project redone and files supplied in JEDEC files with all Sources so that we can then have code that can be modified and transferred if ever needed in the future.
Skills: Field-Programmable Gate Array (FPGA) Circuit Design Embedded Systems
Fixed-Price - Expert ($$$) - Est. Budget: $50 - Posted
The job is simple, I need a way to control clock frequency in ALTPLL IP function in Quartus 14.0 altera FPGA software. Task: I want to use altera fpga bemicro max 10 (10M08DAF484c8GES) push buttons to control the output clocks c0, c1 clocks and respective phase shift in PLL.
Skills: Field-Programmable Gate Array (FPGA) HTML5