Last active: 15 days ago
He is responsible for analysing, understanding andconverting circuit design into physical/layout design of FPGA integrated circuits while at the same time satisfying design requirementsusing available layout design editor tools. His responsibilities also include but not limited to cell up to chip level custom layout, scheduling, integration/automation, floor planning, routing, and verification.
• Lattice Semiconductor Phils., Plaza B, Northgate, Filinvest, Alabang, Muntinlupa (2013 - 2015)
o Sapphire Family
Has experience in ownership and support for integration and verification for Core(PLC, EBR, ASR and DSP), IO ring, Peripheral Interface Controller(PIC), Serializer/Deserializer(SerDes),Clocks(PClk and EClk), Buffers, PLL and eventually a support for the whole full chip verification.
Supported full chip integration through DRC and LVS verification of its Quad/Core.
o 28nm FDSOI Test Vehicle
Worked closely with US counterparts for the implementation of SRAM.
Managed a small group of mask designers for completion of Non-Volatile Configuration Memory(NVCM), Multiplexers, and Leakage circuits.
Worked as a resource for the NVCM, and owned blocks such as NVCM_cell arrays.
Headed mask designers as a top block owner for the External Clock and External Clock buffers.
Conducted training for new hires.
Undergone Place and Route Overview Training
Provided key learning document after each project for Post-Mortem Discussions
Develop automation scripts using SKILL.
Conducted tests and assessments for Antenna, DRC and LVS verifications during tools transition from Calibre to Cadence Physical Verification System.
• Rohm LSI Design Phils. Inc., Ortigas Center, Pasig City (2010-2013)
o Power Management Chips and ASIC’s
Owned block level to top level layout for both analog and digital blocks examples are: current mirrors, temperature shutdown and under-voltage lockout(TSD_UVLO), EEPROM, OTP’s, charge pump, oscillator, amplifiers and bandgap.
• Layout Tools - Jedat Alpha-SX and Cadence Layout Suite
• Verification Tools – Dracula, Calibre and Cadence PVS (DRC, LVS, Physical ERC, Latch-up, ESD, Antenna, Via Charge Up, VPS/EMIR, LVL, Latch-up)
• Cadence SKILL programming