Rajalakshmi S Menon Menon
Last active: 1 month ago
M.E. (VLSI Design), PSG College of Technology CGPA 8.42/10 2014
B.E (ECE) Asan Memorial College of Engg and Tech CGPA 6.95/10 2012
Organization : BASELIOS THOMAS I CATHOLICOSE COLLEGE OF SCIENCE AND TECHNOLOGY
Position : Assistant Professor
Duration : SEPTEMBER 15TH , 2014 TO March 31st 2015
Subject Handled : Digital Electronics
• Cadence Tools - Virtuoso Suite, RTL Compiler, SoC Encounter.
• Hardware Languages- VHDL, Verilog.
• System Generator,Xilinx ISE, Model Sim, MATLAB.
• Mentor Graphics – Eldo, Pyxis Schematic, Pyxis Layout (IC graph), Calibre.
• Tanner Spice Suite - Sedit , Ledit.
• Scripting Language - PERL.
• Software Language – C
• FPGA- Sparten 3e, Virtex II.
• Basic knowledge of UVM , System Verilog , Verilog AMS and VHDL AMS.
Project title : A Low power SerDes Transceiver for On-Chip Networking(PG )
Period : Dec 2013 - May 2014
Tools used : Cadence Virtuoso
Project title :Implementation of NoC Router architectures with different Crossbar structures(PG)
Period : June 2013 – October 2013
Tools Used : Xilinx ISE 14.1, Cadence RTL Compiler and SoC Encounter
Project title : The integration of NoC architecture with classical bus-based system (UG)
Period : December 2011- May 2012
Tools Used : Xilinx 9.2, Sparten 3e
• Implementation of low power analog multiplier using Cadence Virtuoso.
• Implementation of single stage fully differential folded cascode amplifier employing gain boosting technique to obtain high gain.
• Design of KHN filter(Universal/All pass filter)
• Static noise margin analysis of 6T SRAM.
• Implementation of Carry Save multiplier using Multi-Vdd Technique and Single supply Level Converter and its power and area is analyzed using Tanner EDA tool.