You will get verilog vhdl system verilog code on ise vivado quartus modelsim for fpga

Uzair A.
Uzair A. Uzair A.
4.9
Top Rated

Let a pro handle the details

Buy Other Development & IT services from Uzair, priced and ready to go.

You will get verilog vhdl system verilog code on ise vivado quartus modelsim for fpga

Uzair A.
Uzair A. Uzair A.
4.9
Top Rated

Let a pro handle the details

Buy Other Development & IT services from Uzair, priced and ready to go.

Project details

HI! and Greeting everyone.
Are you looking for an expert in FPGA coding and digital logic design? Look no further! I am here to provide you with top-notch services in this field.
-With 5 years of experience in FPGA coding using Verilog, VHDL, and HLS I can help you with all your FPGA design needs.

Design and implementation of combinational and sequential circuits
Modeling of any system or module using verilog, system verilog, and Vivado HLS
Logic reduction using K-Maps.
Finite State Machine (FSM) design
FPGA prototyping and testing & debugging of existing designs
I have worked on a variety of projects, including but not limited to:
ALU, multipliers (Wallace, booth, etc.),
Microblaze, ZYNQ PS + P
Nios II-based systems for Intel FPGAs
Drivers for applications in C and C++
SPI, UART, and I2C interfaces.
Verilog-based ping-pong game
Verilog-based elevator, vending sales machine, ping-pong game & BCD to 7segment display
Software expertise:
LOGISIM
XILINX
VIVADO
MODELSIM
Quartus
Why Choose Me?
-Committed to delivering high-quality work
-Prompt response and Excellent customer service
-If you need help with your FPGA coding or digital logic design projects, please feel free to contact me.
Project Type
Data Analysis, Development, Cybersecurity, Data Protection, IT, File Conversion, User Testing
What's included
Service Tiers Starter
$30
Standard
$40
Advanced
$100
Delivery Time 1 day 2 days 3 days
Number of Revisions
555

Frequently asked questions

4.9
12 reviews
100% Complete
1% Complete
(0)
1% Complete
(0)
1% Complete
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1% Complete
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Rating breakdown
Availability
4.9
Deadlines
5.0
Skills
4.9
Cooperation
4.9
Quality
4.8
Communication
4.9

AS

Alberte S.
5.00
Feb 13, 2025
First Project

AS

Andrii S.
5.00
Dec 30, 2024
30 minute consultation Uzair is very strong engineer. The consultation was extremely helpful and I learned a lot about IC design and manufacturing process. Hope will start a project with him soon

DH

David H.
4.50
Jun 9, 2024
IC Layout Engineers for PDS430 MCU Project Tape-Out Uzair is quite proficient with the Cadence layout tools for full-custom layout projects and was able to deliver his layout blocks on time. Would like to see him improve his skill in the digital domain by gaining more experience and knowledge with logic synthesis and APR.

AP

An P.
4.80
Apr 28, 2024
OpAmp design project

YH

Yousef H.
4.65
Mar 17, 2024
Tutor and professional Electrical Engineer specializing in Analog and Digital Signal Processing
Uzair A.

About Uzair

Uzair A.
Analog/RF/Mixed Signal/ASIC Physical Design/RTL-GDS/ PCB Design Expert
100% Job Success
4.9  (12 reviews)
Charsadda, Pakistan - 4:22 pm local time
Greetings! I am an adept Analog and Digital Circuit Designer, specializing in Integrated Circuit (IC) design. With experience in 5 IC tape-outs utilizing different PDKs such as 28nm, 45nm, 65 nm, 110 nm, 130nm, and 180 nm, my expertise lies in designing and simulating Analog ICs (Schematic to GDSII), Digital ICs (RTL to GDSII), Mixed-signal integrated circuits (SoC), RISC-V Backend Design( RTL-GDSII) and RF ICs (upto 60GHz). Proficient in tools like Cadence Virtuoso, Mentor Graphics Calibre, Cadence Genus, Encounter/Innovus, Synopysis DC compiler, PrimeTime, ICC2, Custom Compiler, VCS, Xilinx, Vivado, Quartuas, Modelsim, Matlab, and OpenSource ASIC design tools like "Openlane." & "Xscheme". Proficient in Programming Language C/C++, Verilog, VHDL, and System Verilog. Eagerly await your response. Thank you.

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Delivery time starts when Uzair receives requirements from you.

Uzair works on your project following the steps below.

Revisions may occur after the delivery date.

step1

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