Karthik M.
HyderabadIndia

Verilog Developer | System Verilog & Cocotb

Experience in RTL design, formal verification, linting, Clock Domain Crossing (CDC), compilation, Design For Test (DFT), Static Timing Analysis (STA), Unified Power Format (UPF), netlist generation, VLSI design flow. Languages: Verilog, System Verilog, Python Programming, CocoTB, Assembly, x86, nios Terminal: bash, csh, sh Operating System: Unix, Linux Softwares: Synopsys Spyglass, VCS Cadence, Intel Quartus Prime, Questasim, eSim, KiCAD, OpenLANE, OpenRoad, YoSYS, SymbiYOSYS, SimVision, Verdi Integrated circuit (IC) design, Printed Circuit Board (PCB) designing. Efficient power supply circuit with professional circuit designs

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Skills

  • Hardware Description Language
  • Digital Electronics
  • Digital Pattern Design
  • Research Protocols
  • Communications
  • Digital Design
  • Electronics
  • Python Script
  • Linux