FPGA Engineer

FPGA Engineer About Digis We are a European IT company with 200+ specialists delivering SaaS platforms, enterprise solutions, and cloud-native products for clients worldwide. We focus on building strong, long-term teams and supporting continuous professional growth. About the Project Our client is looking for an experienced Timing Closure Specialist with strong Verilog expertise for Intel (Altera) FPGAs (Cyclone 10 GX). They're seeking an engineer who enjoys solving complex timing issues, optimizing FPGA implementations, and improving build efficiency. If timing closure is your area of expertise, we'd love to hear from you. Responsibilities -Diagnose and resolve timing issues—path delays, clock skew, routing congestion—in Altera builds. -Refactor Verilog code, optimize constraints, and refine architectures to minimize seeds and accelerate timelines. -Leverage Intel Quartus Prime for static timing analysis, ensuring robust, high-performance designs. Requirements -3+ years of commercial experience with Verilog FPGA design and strong expertise in Intel (Altera) FPGAs. -Proven experience resolving complex timing closure issues and optimizing FPGA builds to reduce compilation iterations. -Strong understanding of synchronous digital design, Clock Domain Crossing (CDC), and high-speed interfaces. -Hands-on experience with ModelSim or similar simulation and verification tools. Working hours: 5–6 hours of overlap with the client's working hours, starting at 9:00 AM Hong Kong Time (HKT).