6-Layer Raspberry Pi CM5 Carrier PCB — Full Design from Written Spec to Fab-Ready Gerbers (KiCad)

I'm building a controller board for a residential solar + battery energy system and I'm hiring an experienced PCB designer to take it from my written specification to fab-ready Gerbers. This is a complete, clean design job — schematic capture, stackup, placement, routing, verification, and manufacturing outputs — done thoroughly, with review gates where I sign off before you proceed. I have a strong electronics background (STM32, CAN, rework) and I know exactly what I want this board to do. What I'm buying is disciplined, professional execution of the design itself. I've already turned down a cheap design-service quote because I want someone who treats verification as part of the job, not an afterthought. The board (so you can scope your bid honestly): Raspberry Pi Compute Module 5 (CM5) carrier — high-density board-to-board connector escape ESP32-S3 module as a real-time co-processor — its Wi-Fi radio is a live production feature: module placement/orientation and antenna keep-out (all copper layers) per Espressif's guidance are required, not optional ~200 × 150 mm outline, 6-layer, ENIG, 5/5 mil — standard fab capability, no HDI Controlled-impedance differential pairs: Gigabit Ethernet (magjack), HDMI, USB, MIPI DSI display Isolated comms section: RS-485 and CAN with a 5 mm creepage/clearance barrier Small analog front end (instrumentation amp / precision measurement) All low-voltage DC on-board: 12 V input, 5 V and 3.3 V rails (5 A-class pours) Connector-dense perimeter: 16-position Phoenix field-wiring terminal plus numerous headers and jacks Roughly 230–250 components, most already selected for LCSC/JLCPCB assembly availability What you get from me on day one: A written block-level specification of every subsystem A complete parts list with manufacturer part numbers (and LCSC numbers where available) A pin-by-pin connector/interconnect table for every off-board connection Mechanical envelope, mounting hole positions, and connector edge assignments Datasheets for every non-trivial part You will not receive prior CAD. This is a deliberate from-scratch redraw from the spec — I want your independent engineering judgment on the schematic and layout, not a cleanup of someone else's files. If the spec is ambiguous or you think a part choice is wrong, I want you to flag it and argue with me. That's the thoroughness I'm paying for. Scope of work / milestones (quote per milestone): Schematic + BOM — full hierarchical schematic in KiCad with live symbol/footprint associations, ERC-clean, plus your review notes on my part choices. I review and sign off. Stackup + placement — documented 6-layer stackup with impedance calcs for the controlled pairs, floorplan and full placement, isolation barrier defined. I review and sign off. Routed board + verification report — 100% routed, 0 DRC / 0 unconnected, plus the verification pass described below. Pre-Gerber review; I sign off. Manufacturing package — Gerbers + drill files, stackup/impedance spec for the fab, BOM (CSV/XLSX with MPN + LCSC), pick-and-place/CPL, PDF schematic, 3D STEP export, and support answering fab/assembly DFM questions through order placement. Bringup support — reasonable availability (email/calls) for 2–4 weeks after assembled boards arrive to help debug first power-on issues. Definition of done — this is the important part. Passing DRC is necessary but not sufficient. Before Milestone 3 is accepted, I expect: Every connector pinout verified against my interconnect table, pin by pin Every footprint verified against the actual sourced MPN's package drawing Power nets verified for copper width/pour against their current rating (not just netclass defaults) No unnetted or dead pads; schematic and board in full parity Test points on every power rail, 3 fiducials, per-pin silkscreen labels on field-wiring terminals, isolation barrier marked on silk ESP32-S3 antenna keep-out honored on all layers, antenna oriented toward free space (Wi-Fi is a shipping feature) Connector placement matches the provided edge-assignment map (the board mounts in an enclosure; cable directions are fixed) A short written verification report saying you actually did these checks Tools: KiCad required (v9/v10 — native project files are a deliverable; I maintain this board myself afterward). Please don't bid if you only work in Altium/OrCAD. Timeline: No hard deadline — propose a realistic schedule in your bid. I will pick thorough over fast every time. Budget: Quote me a fixed price broken down by the 5 milestones above (or hourly rate + estimated hours if you strongly prefer), along with your calendar estimate. I'm paying for expert work and expect to pay expert rates; lowball bids that don't engage with the spec above will be ignored. In your proposal, please include: 2–3 boards you've designed that are comparable — ideally a CM4/CM5 or other SoM carrier, or any 4–6 layer board with high-density BGA/mezzanine escape and controlled-impedance pairs. Images or links. The checks you personally run beyond DRC before releasing Gerbers. How you handle isolation/creepage requirements for isolated comms sections. Your milestone pricing and timeline. So I know you read this far and you're not a bot: start your proposal with the word MAGJACK.