PCB Altium Designer: 12+ Layer FPGA Board, 12.5 Gbps, Impedance Controlled + Length Matched

We are looking for an experienced PCB layout engineer for the LAYOUT phase (detailed placement + routing) of an FPGA-based test & measurement board. The schematic is complete and reviewed. A rough placement (floorplan level: board outline, connector and mounting positions, main IC locations, power zones) is done in-house and will be provided as the starting point. Your job: detailed component placement within that floorplan, fanout, routing, planes, and rule-clean DRC. The project ----------- - EDA tool: Altium Designer (native project files provided; work stays in Altium, no conversion) - FPGA: AMD/Xilinx UltraScale+ (Kintex), BGA in SFVB784 package, 784 balls, 0.8 mm pitch - 2x FMC (VITA 57.1) connectors: high pin count, approx. 260 single-ended/differential fabric signals, length matched per interface group - High-speed serial: 14 GTY transceiver lanes up to 12.5 Gbps (FMC data pairs + 1x SFP+ cage + on-board loopback), 100 ohm differential, impedance controlled - Clocking: multiple LVDS reference clock pairs - Power: approx. 15 power domains (11 regulated rails, incl. one high-current FPGA core rail, plus switched/monitored port rails); several DC/DC converters with defined layout rules - Precision analog: Kelvin-connected current shunt measurement paths (rules provided; must be followed exactly) - Board class: approx. 200 x 150 mm, 12 or more layers, 1.6 mm, through-via only (no HDI, no backdrill), stackup and impedance targets will be defined with designer - Design size: 117 BOM line items, 915 components total, approx. 600 nets - Length matching: matched-length groups defined per interface; - No DDR memory interfaces on this board