Place and route a 4-layer Rockchip Linux board in KiCad 10 (schematic complete and verified)

I have a complete, ERC-clean KiCad 10 project for a consumer smart-device mainboard and need an experienced layout engineer to do the component placement and routing. The schematic, verified BOM (LCSC part numbers), project libraries, netlist, and a detailed written constraints document are all ready. You start from a clean board: parts placed as a reference only, zero routing, all requirements documented. The board: Rockchip RK3506G2 SoC, QFN-128 at 0.35 mm pitch (fine-pitch escape routing is the core challenge) 179 placed parts plus 4 mounting holes, 135 routable nets, about 476 connections, currently 88.6 x 68 mm (may shrink, must not grow) 3x MIPI DSI differential pairs at 100 ohm to a 40-pin display FPC 2x USB 2.0 pairs at 90 ohm (one to a connector, one to the Wi-Fi module) 2.4 GHz Wi-Fi/BT module with 50 ohm u.FL antenna feed Li-ion power path: charger, fuel gauge, three bucks, two boosts, power latch Mixed signal: audio codec plus speaker amp, and a 24-bit load cell ADC that needs a quiet analog zone Target: 4 layers on JLCPCB's impedance-controlled stackup (JLC04161H-7628). If you conclude 4 layers cannot close cleanly, 6 layers is pre-approved, but try 4 first. Deliverables: Routed KiCad 10 project: zero DRC errors, zero unconnected nets, using the design rules shipped with the project, DRC report included JLCPCB fabrication package: gerbers, drill, BOM, and CPL for their economic SMT assembly Stackup choice and impedance calculations for the controlled nets Short design note listing anything you changed or could not honor Tools: KiCad 10 required. The project files are v10 format and will not open in KiCad 9 or older. Delivery in KiCad 10 format. Confidentiality and IP: standard Upwork terms apply: the layout work is work-for-hire and all rights in the deliverables transfer on payment. Please do not share the package or reuse the design files. What you get from me: a self-contained KiCad 10 project (custom libraries included; generic passives use the standard KiCad 10 libraries), schematic PDF, netlist, a thorough constraints README (edge connector assignments, plane strategy, netclass and design-rule tables, decoupling and analog rules, verification checklist), and fast answers to questions. You are a fit if you have: shipped boards with MIPI DSI or similar high-speed differential pairs, fine-pitch QFN/BGA fanout experience, switching-regulator layout experience, and comfort delivering in KiCad. RK35xx family or JLCPCB assembly experience is a plus.