Hire the Best Beamex CMX Specialists

I turn point clouds into verified, construction-grade BIM deliverables. 8+ years in the AEC industry, including 4+ years in reality capture on gigaprojects in Saudi Arabia and the UAE, plus 85+ scan-to-BIM models delivered to US clients as a production partner to Integrated Projects (New York), working with Matterport data. Currently leading scan-to-BIM QA/QC on two major entertainment complexes, with 700+ LOD 500 models under verification and hundreds of scan setups processed, cleaned, and exported every month. What I deliver: -Point cloud data processing — Registration (Leica Cyclone Register 360, Trimble RealWorks, FARO SCENE, Autodesk ReCap), cleaning, noise removal, classification, decimation/subsampling, coordinate system alignment, and format conversion (LGS/LGSx, E57, RCP, PTS, LAS). I handle large multi-setup terrestrial datasets and UAV photogrammetry data daily, on a dedicated high-spec workstation. -Matterport to BIM — Matterport/E57 exports to Revit as-built models. 85+ residential and commercial units delivered to US-based clients over a two-year partnership, working to standardized modeling specs on bi-weekly production cycles. -Scan-to-BIM modeling & QA — Point cloud to Revit as-builts at LOD 300–500, modeled to your tolerance spec, with documented compliance. -Cloud-vs-BIM deviation analysis — Element-by-element tolerance checking (Leica Cyclone 3DR) with colour-mapped deviation reports ready for consultant submission. This is my core specialty: ---I've built automated pipelines that produce formal verification reports in hours, not days. -Cyclone 3DR automation scripting — Custom JavaScript tools for batch import, tolerance checking, reporting, and pipeline automation. If your team owns 3DR and does anything repetitive in it, I can script it. -UAV photogrammetry processing — Metashape/Pix4D reconstruction, orthomosaics, terrain models. Why clients work with me: I sit on the contractor side of real projects, so I know what consultants reject and why. My reports don't just show deviations — they're structured to pass formal review. Fast turnaround and clear communication in English. Mechanical Engineering BEng (Heriot-Watt University). Based in Saudi Arabia (GMT+3) — convenient overlap with EU, UK, and Australian hours.

I am a highly experienced digital design engineer with 4+ years of professional expertise in ASIC and FPGA design. I specialize in RTL coding using Verilog, VHDL, and SystemVerilog to deliver high-performance, optimized hardware solutions. My technical toolkit includes: - FPGA Design: Vivado, ISE, Diamond, Quartus - ASIC Design: VCS, DVE, DC, Formality, Spyglass - HDL Languages: Verilog, SystemVerilog, VHDL - Design Optimization: Speed, area, and power optimization - Simulation & Verification: Comprehensive testbench development - Tools: Cadence Platform, ModelSim, VCS I have successfully delivered 47+ complex projects including FPGA-based image encryption systems, efficient matrix multiplication designs, Bitcoin miners, and advanced processor architectures. Every project is delivered on time with detailed documentation and verification. Clients appreciate my clear communication, attention to detail, and commitment to creating efficient, production-ready designs. Whether you need RTL coding, synthesis optimization, or full design implementation, I'm ready to help!

I am an expert in SystemVerilog, Verilog, and VHDL with over 5 years of experience in FPGA and IPS verification using Cocotb and UVM. For IPS verification, I primarily use the Cocotb and UVM libraries. Some highlights of my experience include: 1. Working with simulators such as Xilinx Vivado, Cadence, Synopsys, Icarus, and Verilator. Assisting with digital system design projects, including building data paths and control units using Verilog. 2. Extensive experience with microprocessor projects; if you’re looking for an expert in this area, I can help. 3. Proficiency in assembly coding on the Edsim51 simulator using 8051 assembly language. 4. Strong command of C and C++ for related projects. 5. "I am skilled in RISC-V processor design and implementation on FPGA boards. I have expertise in developing, configuring, and deploying RISC-V architectures, enabling efficient and customized processor solutions on FPGA hardware."

Robots that don't know where they are, can't navigate reliably, or fail when moved from simulation to real hardware — these are the problems I solve. I specialise in the full autonomy stack for mobile robots: LiDAR and Visual SLAM for mapping and localisation, Nav2 configuration and tuning for reliable navigation, multi-robot simulation across Gazebo Classic, Gazebo Harmonic, and Isaac Sim, and perception pipelines for detection and scene understanding. My background is Computer Engineering with an MSc in AI — I work equally well on research platforms and production deployments. WHAT CLIENTS TYPICALLY HIRE ME FOR ☑ SLAM that doesn't drift — LiDAR-inertial (solid-state and mechanical), RGB-D, monocular, and visual-inertial pipelines on real hardware ☑ Nav2 that actually works — Ackermann, differential-drive, and tracked robots, including the failure modes that generic tutorials don't cover ☑ Multi-robot simulation — namespace isolation, TF management, QoS configuration for 5-10 robot systems across Gazebo Classic, Harmonic, and Isaac Sim ☑ Perception integration — real-time object detection, point cloud segmentation, thermal inspection, published as ROS 2 topics for downstream use ☑ Sensor fusion — EKF tuning, IMU characterisation, LiDAR-camera extrinsic calibration ☑ Consulting and technical advisory — architecture review, root cause diagnosis, and implementation roadmaps for SLAM, navigation, and simulation projects HARDWARE I HAVE WORKED WITH DIRECTLY ☑ Unitree L2 solid-state LiDAR ☑ Intel RealSense RGB-D camera ☑ FLIR AX8 thermal camera ☑ RPLiDAR A-series (2D mechanical LiDAR) TRACK RECORD 100% Job Success Score. 5-star reviews on all completed contracts. HOW I WORK I take fixed-price and hourly contracts. Before starting any project I ask the questions that prevent wasted weeks — what sensor, what environment, what the failure looks like, and what the real constraint is. That diagnostic step is usually where the value is. I also take consulting engagements alongside implementation work — architecture review, root cause diagnosis, and technical direction for anyone who needs an outside perspective on why something is not working.

Greetings! I am an experienced Civil Engineer and a Drone Mapping and Photogrammetry Specialist. Services that I offer - Drone Photogrammetry (2D and 3D Aerial Mapping) - 3D Mesh, Orthomosaic, Orthophoto - DEM, DSM, DTM, Contours, Volumetrics - Lidar (Topographic Survey) - Scalable Terrain Model - Point Cloud (Registration, Alignment, Classification, Feature Extraction and Segmentation) - Point Cloud to BIM - CAD - Planimetrics - Building Inspection, Tower Inspection, Bridge Inspection, Construction Monitoring - Digitized Map - Structural Analysis and Design - Quantity Surveying Programs that I use - Bentley iTwin Capture (ContextCapture) - Agisoft Metashape - DroneDeploy - Pix4D - Reality Capture - DJI Terra - CloudCompare - TerraScan - Global Mapper - QGIS - OpenRoads Designer - AutoCAD Civil3D - Blender - LumenRT - Revit - Staad.Pro - MicroStation - AutoCAD - Bentley Descartes - Orbit 3DM (Manage and Extract) - Sketchup - Planswift

Senior FPGA engineer with 10+ years of hands-on design and verification experience, specializing in high-speed networking, SoC development, and open-source FPGA frameworks. Recent work includes: - 5G O-RAN Fronthaul on Xilinx UltraScale+ (eCPRI, 25G Ethernet, JESD204B) - RISC-V SoC debug transport over PCIe on AMD Alveo (LitePCIe, LiteX/Migen) - Ethernet packet scheduler and rate limiter using LiteX/LiteEth (10G, AXI4-Stream) Core strengths: - FPGA platforms: Xilinx/AMD UltraScale+, Alveo, Kintex, Artix · Zynq-7000 · Intel/Altera Cyclone - High-speed interfaces: 10G/25G Ethernet, PCIe (XDMA, LitePCIe), JESD204B, GTH/GTY - Frameworks: LiteX/Migen, Cocotb, Vivado, Quartus - Protocols: AXI4/AXI4-Stream, Wishbone, O-RAN 7.2x, IEEE 802.3, PTPv2 - Verification: UVM, Cocotb, formal verification (VC-Formal, JasperGold), VCS, Xcelium - Languages: SystemVerilog, Verilog, Python, C Available for remote engagements. Comfortable working async across time zones.