ESP32 Ventilation Control Unit (CU) PCB

1. Overview Design the PCB for an industrial supply/exhaust ventilation controller (DIN-rail / panel mount). This is a re-spin of an existing ESP32-WROOM-32 board: the MCU is upgraded to ESP32-S3, with new connectivity and hardware-safety features added. All other functional blocks keep the same function and composition as the original board unless stated otherwise. A companion LCD panel (not part of this order) connects to the board by cable (power, Modbus over RS-485, and a UART pass-through for flashing the LCD). 2. Scope of work The scope is the full design cycle of the controller PCB: Schematic capture on the ESP32-S3. Footprint creation/verification and component selection with availability in mind. PCB layout to the outline and form factor in Section 4. Preparation of the manufacturing and assembly file set (Section 8). Design-review checkpoints with the client at "schematic done" and "layout done" stages (before releasing manufacturing files). Out of scope: board fabrication and assembly, firmware development, LCD panel design. (Optional, by separate agreement: support during production bring-up.) 3. Provided by the client Source files of the existing board in DipTrace format (schematic .dch + board .dip) as a reference for "which blocks to keep". A detailed functional-block brief (this document is its formalization). Prompt answers to questions and decisions on any open points (Section 10). 4. Mechanical and form factor Board outline: 123 × 88 mm, rectangular. 4× M3 mounting holes, one near each corner, with copper keep-out, for DIN-rail or panel mounting. Field connections via screw terminals along the board edges, grouped by function. Clear silkscreen for every block: K1..Kn, AO1..AO4, DI1..DIn, SAFETY, RS485 A/B, 1-WIRE, I2C, ETH, 12V IN, USB, LCD. 5. Block-level technical requirements 5.1 Microcontroller ESP32-S3-WROOM-1U-N8R2 module (8 MB flash, 2 MB PSRAM, EXTERNAL antenna via IPEX/U.FL). The external Wi-Fi antenna is brought out to the enclosure/panel wall via the module's on-board U.FL and an off-the-shelf U.FL → RP-SMA (bulkhead) pigtail. No PCB footprint is required for this — it is an enclosure-mechanics matter. Programming/debug only over native USB-C (USB-Serial-JTAG, GPIO19/20; also a power input). No separate controller UART header is required. EN/RESET tactile button — fitted (for manual restart in the field without USB), with an EN pull-up to 3.3 V and a reset capacitor. BOOT (GPIO0) — no button; bring out to plated through-holes (THT) for a solderable pin (with an adjacent GND hole) and a strapping pull-up. The holes allow soldering a pin header or tacking a wire/jumper if needed. Normal flashing is over USB-Serial-JTAG without BOOT; emergency bootloader entry is by pulling GPIO0 to GND at power-up. Respect ESP32-S3 reserved pins: USB (19/20), strapping (0, 3, 45, 46), the module's internal flash/PSRAM pins. UART0 (43/44) is free (see Section 6). 5.2 Power Primary input: 12 VDC via screw terminal, with reverse-polarity protection (P-FET ideal diode or series diode) + TVS, plus an input fuse or resettable PTC. 12 V → 3.3 V via a switching buck regulator (not an LDO — at 12 V in with a Wi-Fi+Ethernet load the LDO dissipation/heat is unacceptable) for the MCU and logic. The 0–10 V output stage runs directly off the 12 V rail (rail-to-rail op-amps able to swing a full 0–10 V on a 12 V supply). USB-C 5 V diode-OR'd into the logic supply (run/flash from USB alone). Isolated 5 V branch for the RS-485/LCD domain (from the isolated transceiver's DC-DC or a separate isolating converter), sized to power the LCD panel; see Section 5.6. USB-C as a power sink: 5.1 kΩ pull-down resistors on CC1 and CC2 (mandatory, otherwise the port is not detected and will not deliver 5 V). Power LED; decoupling and bulk capacitors; test points for 12 V / 3.3 V / GND. 5.3 Inter-board connector to the LCD panel (free-form cable) One connector carrying: 5 V, GND, RS-485 A, RS-485 B, LCD_UART_TX, LCD_UART_RX. Purpose: the controller powers the LCD, talks Modbus to it (RS-485 A/B), and passes the LCD's own UART through so the LCD can be flashed via the controller. LCD_UART_TX/RX are pass-through only (connector → LCD flashing header, Section 5.4); they do not consume MCU GPIOs. 5.4 LCD flashing header The controller itself is flashed over USB-C, so it has no UART header of its own. One header exposing the passed-through LCD_UART_TX/RX (from the inter-board connector, Section 5.3) — to flash the LCD panel via the controller. Pin order and connector type are at the designer's discretion (cable wires are re-arranged to the actual pinout); only clear signal labeling on the silkscreen matters. 5.5 Ethernet (10/100) WIZnet W5500 over SPI (SCLK, MOSI, MISO, CS, INT, RST) + a 25 MHz crystal (with correct load capacitors). RJ45 with integrated magnetics, link/activity LEDs, Ethernet ESD/TVS. Impedance control on the Ethernet differential pairs (see Section 7). 5.6 RS-485 / Modbus RTU (field bus, master) — galvanically isolated Isolated RS-485 transceiver (3.3 V), half-duplex, DE+RE tied to one GPIO. Galvanic isolation between MCU logic and the bus: digital isolator on TX/RX/DE + an isolated DC-DC for the bus-side supply. An integrated part with built-in isolated DC-DC is acceptable (e.g. ADM2587E / ADM2682E or equivalent) — then no separate isolating converter is needed. A/B screw terminal (+ isolated bus GND), jumper-selectable 120 Ω termination, fail-safe bias resistors, TVS on A/B. (9600 8N1.) The same A/B pair goes to the inter-board LCD connector — the LCD is a node on this same bus. LCD domain: since the LCD is powered by the controller and sits on the same bus, place the LCD connector (A/B and its 5 V/GND) on the isolated (field) side — power the LCD from the isolated 5 V so the logic isolation is not defeated. Size the isolated DC-DC with margin for the LCD current (including backlight). The reference ground of the LCD flashing header (LCD_UART pass-through) is also on the isolated side; note that an external USB-UART cable temporarily bridges the domains during flashing. 5.7 Status LEDs (3×, MCU-controlled) Indicator LEDs on GPIOs: "network", "error/fault", "LCD link". The power LED is separate and hardwired to the rail. 5.8 Relay outputs (K1..Kn) SPDT relays, NO/COM (NC if room) to per-channel screw terminals, flyback diodes. ULN2803A driver (8 channels per package), GPIO HIGH = ON. Maximize the number of relays within the board area and edge length available for terminals. Minimum 4. Channel assignment is set by firmware — not fixed in hardware; silkscreen K1..Kn is neutral. By default the driver channels are controlled directly from MCU GPIOs. An I2C port expander is the fallback: use it only if the desired relay+input count exceeds the free pins (relays are not timing-critical). 5.9 Analog outputs 0–10 V (AO1..AO4) Per channel: MCU PWM (LEDC ~10 kHz) → RC low-pass → non-inverting op-amp gain to 0–10 V (12 V rail, rail-to-rail), series output resistor / short-to-GND protection. A "signal + GND" screw terminal per channel. Channel assignment is set by firmware — not fixed in hardware. Choose an op-amp with a guaranteed output swing of ≥10.5 V on the 12 V rail (load = high- impedance 0–10 V control inputs). 5.10 Digital inputs (DI1..DIn), dry contact Opto-isolated, active-LOW, input current limit + RC debounce + TVS, per-channel screw terminals + a common. Maximize the number of inputs within the board area and edge length available for terminals. Minimum 5. Input assignment is set by firmware — not fixed in hardware; silkscreen DI1..DIn is neutral. By default inputs are read directly from MCU GPIOs. An I2C port expander is the fallback: use it only if the desired relay+input count exceeds the free pins (signals are slow — limit switches, dry contacts — so expander latency is acceptable). 5.11 Hardware safety interlock (trip independent of the MCU) A normally-closed safety loop (screw terminals) for field safety contacts (coil freeze-stat, high-pressure switch, fire alarm). The loop is conditioned (debounced) into a LOOP_OK signal (high = loop closed = OK). Hardware latch with set-dominant priority. When the loop opens, the latch instantly drops ENABLE (outputs go off) and latches that state — ENABLE stays low even after the loop re-closes (no automatic restart). The entire critical path is discrete logic/relay, with no MCU involvement: outputs drop even if firmware hangs. Output gating with per-channel jumper selection. ENABLE drives a power switch (MOSFET / power relay) feeding a "gated rail". Each relay (K1..Kn) and each 0–10 V output has a jumper selecting power from the gated rail (output is in the safety group, killed on a fault) or from the always-on rail (output independent of safety). This lets any single output, all outputs, or any subset be in the group. The 0–10 V op-amp stage is disabled by the same ENABLE (removing gated-rail power from the stage / an analog switch on the output — designer's choice). Re-arm (re-enable) — from the ESP only, not automatic. The ESP issues an opto-isolated pulse to re-arm, which is effective only while the loop is closed (LOOP_OK high) and only as a deliberate operator command (not an auto-restart). The set-dominant latch guarantees the ESP (or any stuck signal) cannot enable outputs while the loop is open. There is no local backup reset: with the ESP non-functional, outputs stay off (safe state — accepted by design). The MCU reads loop and latch state (LOOP_OK/ENABLE) via an opto-isolated input (cannot override the protection); shown on the "error/fault" LED. Fail-safe field wiring: wire outputs so that a de-energized relay = safe state (motors/actuators stopped). This is a functional hardware interlock, without formal certification (PL/SIL). A discrete solution is acceptable; a certified safety-relay module is not required. 5.12 1-Wire (DS18B20) One 1-Wire GPIO, 4.7 kΩ pull-up to 3.3 V, ESD, 3-pin screw terminal (3V3/DATA/GND), up to 4 sensors in parallel. 5.13 I2C (SCD4x sensor + port expanders) 3.3 V I2C (SDA/SCL) with pull-ups + ESD, a 4-pin Qwiic/JST-SH connector (3V3/GND/SDA/SCL). On the bus: the SCD4x CO2/T/H sensor (0x62) and — if needed (fallback per Section 5.8/5.10) — port expanders for digital inputs and/or relay control. Use as many PCF8574/PCF8574A as needed (8 lines per package; addresses 0x20–0x27 and 0x38–0x3F) — allocate addresses without clashing with the SCD4x (0x62). With many I/O, account for I2C bus loading and raise the clock / strengthen pull-ups if necessary. 5.14 General requirements ESD/TVS on every field-facing line (RS-485, DI, safety loop, 1-Wire, I2C, Ethernet, USB, power). Decoupling capacitors on every IC power pin; bulk capacitors per rail. Connectors grouped by function. 6. Pin budget and the I/O-count limiter (agree BEFORE layout) Before layout the designer provides a pin-assignment table for the ESP32-S3 and confirms it fits the broken-out pins of the WROOM-1U-N8R2, avoiding strapping (0/3/45/46) and USB (19/20). Fixed peripherals take ~20 pins: W5500 SPI 6, RS-485 3, AO PWM 4, status LEDs 3, 1-Wire 1, I2C 2, safety (opto state input + opto re-arm pulse) 2. UART0 (43/44) is free (preferably reserved for a debug console). Relays and digital inputs are direct-to-GPIO by default. That leaves roughly ~10 free pins for them, enough for modest counts (on the order of 4–6 relays + 5–8 inputs). I2C port expanders are only a fallback: use them if more I/O is needed than free GPIOs allow. In practice the limiter is reached first by the board area and the edge length available for screw terminals (123 × 88 mm with many field connections). The designer proposes the final relay and DI counts at the architecture review and justifies them. 7. Design and quality requirements Layer count: at the designer's discretion (likely 4 layers), with justification. Clean DRC/ERC with no violations; rules per the chosen fabricator. Impedance control on the Ethernet diff pairs; correct W5500 and 25 MHz crystal layout. Wi-Fi / U.FL antenna area — no copper under the RF path, correct RF section. Separation of the "noisy" power/field section from the sensitive analog (0–10 V) and digital. DFM/DFA for assembly; standard 1.6 mm thickness, HASL/ENIG — to be agreed. Clear silkscreen, fiducials, board revision marking. 8. Deliverables #ItemFormat1SchematicPDF + editable source files2Board (layout) fileeditable project source files3Manufacturing filesGerber (RS-274X / X2) + Excellon drill4Bill of materials (BOM)XLSX/CSV, with manufacturers and part numbers5Assembly placement filePick-and-Place (centroid)6Assembly drawingPDF7Board 3D modelSTEP8DRC/ERC reportsPDF/log9MCU pin-assignment tableXLSX/PDF Design tool — KiCad or Altium (KiCad preferred for portability). All editable source files are handed over to the client and are the client's property. 9. Acceptance criteria Schematic and layout pass client review at the checkpoints. DRC/ERC clean; rules match the chosen fabricator. All blocks in Section 5 implemented; pin assignment agreed (Section 6). Implementation matches the agreed decisions in Section 10. The full deliverable set (Section 8) is provided in the listed formats with source files. All BOM parts have valid, purchasable part numbers (or documented alternates). 10. Agreed key decisions All major architectural decisions are fixed: Controller flashing — USB-C only; EN button fitted, BOOT on through-holes for a pin (Section 5.1). RS-485 — galvanically isolated; LCD domain on the isolated side (Sections 5.6, 5.2). Relays and digital inputs — direct-to-GPIO by default; I2C expander only as a fallback when pins run out. Counts maximized to the board/edge limit (Sections 5.8, 5.10, 6). Safety interlock — hardware set-dominant latch, per-channel jumper gating, re-arm from the ESP only as a deliberate command with the loop closed, no local reset, no formal certification (Section 5.11). 11. Terms Timeline: [state target date / milestones]. Budget / payment: [state; milestone-based payment recommended: schematic → layout → file release]. Rights: all source and manufacturing files transfer to the client; the designer retains no exclusive rights. Confidentiality: project materials are not shared with third parties. Warranty: correction of design errors found during fabrication/testing of the first batch is within scope. 12. What to include when applying Examples of similar boards: ESP32/Wi-Fi (antenna, U.FL), mixed-signal (0–10 V op-amp outputs), industrial interfaces (RS-485/Modbus, Ethernet/W5500), functional safety. Design tool used. Milestone-based time and cost estimate, and any clarifying questions on the spec.