FPGA Design Engineer (SystemVerilog / Zynq UltraScale+)

Description We're a deep-tech startup building an adaptive smart windshield (autonomous defog / de-ice / anti-glare) controlled by an AMD Zynq UltraScale+ MPSoC (ZCU104, XCZU7EV). The safety-critical actuation logic lives in FPGA programmable logic; sensor fusion and vision run on the ARM cores. The RTL already exists — this is not greenfield. We have ~10 SystemVerilog cores (PWM heater drive with slew limiting, electrochromic tint H-bridge with fail-safe bleach, hardware safety interlock with fault latching, environmental FSMs, AXI4-Lite register file, AXI4-Stream telemetry FIFO, SPI and I²C masters, integration top), plus cocotb testbenches and cycle-accurate Python golden models that already pass. We need an expert to take this from "verified in simulation" to "synthesized, timing-clean, and running on the board." Scope / Milestones Milestone 1 — Verification run + RTL review (fixed price) Stand up a proper sim environment (Python ≤3.13, Icarus Verilog ≥12 or Verilator), run the full cocotb suite against the RTL, fix any failures, and deliver a short written review of the cores (CDC, reset strategy, lint issues, synthesis risks). Milestone 2 — Vivado synthesis & timing closure Out-of-context synthesis for all cores on xczu7ev-ffvc1156-2-e, resolve timing/utilization issues, deliver clean reports. Our Tcl build scripts exist as a starting point. Milestone 3 — Zynq PS integration → bitstream Block design with Zynq US+ PS wrapper, AXI interconnect to our register file, DMA path for the telemetry stream, final XDC pinout (mezzanine schematic will be provided), full bitstream that boots on the ZCU104. Milestone 4 (likely extension) — Hardware bring-up support Remote support validating PWM/H-bridge outputs, SPI ADC and I²C sensor channels, and the safety interlock against real power electronics on our bench. Hard requirements (filtering applies) -Expert SystemVerilog with delivered Zynq / Zynq UltraScale+ projects — please link or describe at least one PS+PL design you took to a working bitstream. -AXI4-Lite and AXI4-Stream design experience. -cocotb (or strong willingness — testbenches exist, you'll extend rather than write from scratch) and good Python. -Vivado through constraints and timing closure. -Comfortable working from an existing codebase: a generated YAML→SV register contract, golden Python models, and READMEs document the design. To apply, please answer -Describe a Zynq/Zynq-US+ project where you owned RTL through bitstream. What was the hardest timing or integration problem and how did you solve it? -Have you used cocotb? If not, what's your verification methodology? -One critical behavior in our design: with software commanding maximum PWM duty, the hardware interlock must force outputs off and latch a fault on an over-temp trip — independent of software. In 3–5 sentences, how would you structure that logic so it's robust and auditable? -Your availability (hrs/week) and time zone.