Hardware Engineer to Clone LoRa Module (STM32WLE5 / ST MB1791) for JLCPCB SMT Assembly

We are looking for an electronics design engineer to create a 1:1 functional and physical clone/drop-in replacement for the MAC32WLE5 LoRa module. This module is based heavily on the STMicroelectronics MB1791 reference design utilizing the STM32WLE5 System-on-Chip (SoC). Because the architecture is already defined by ST's reference design, this is primarily a replication and optimization task. The final files must be fully optimized for turnkey manufacturing and SMT assembly at JLCPCB. Project Requirements & Technical Scope: Form Factor & Pinout: Must be an exact 1:1 physical clone (identical outer dimensions, castellated holes/pins, and pin assignments) so it drops perfectly onto our existing mainboards. RF Architecture: * Replicate the original RF matching network and path from the reference design. No onboard antenna; the external antenna path must rout to the designated castellated pin just like the original module. Crucial: You must calculate and adjust the RF trace widths/coplanar waveguide to achieve a 50-ohm impedance based specifically on JLCPCB’s standard 4-layer PCB stackup. Component Selection: Maintain identical core specifications (TCXO configuration, internal SMPS power routing). All passive components, crystals, and the SoC must be mapped to in-stock parts from the LCSC / JLCPCB parts library to ensure seamless automated assembly. Shielding: Include the PCB footprint/pads for a standard surface-mount metal shielding can frame over the RF/MCU section, matching the original module's layout. Deliverables Required: Schematics & PCB Layout Files (Preferred in KiCad or EasyEDA Pro). Manufacturing Files: Production-ready Gerber files, Drill files, and Stencil layout. JLCPCB Assembly Files: Fully mapped BOM (Bill of Materials) with LCSC part numbers and a CPL / Pick-and-Place (Centroid) file. 3D STEP File of the completed module. Milestones ($200 Total): Milestone 1 ($100): Schematic completed, JLCPCB parts selected, and initial PCB component placement approved (verifying physical size and pinout compatibility). Milestone 2 ($100): Completed 4-layer RF routing, impedance calculations verified, and delivery of all manufacturing/assembly files (Gerbers, BOM, CPL). How to Apply: Please start your proposal with the word "LORA50" so I know you read the full description. Briefly mention your experience with the STM32WLE5 or sub-GHz RF layout, We want this in Kicad , and your familiarity with preparing files for JLCPCB SMT assembly.