PCB Layout & Schematic for 38.5mm Circular BLE/Dual-RFID Carrier Board

Project Description: I require an Electrical Engineer to design a custom schematic and PCB layout for a highly compact, circular carrier board. The design must be optimized for immediate PCBA manufacturing via JLCPCB. Physical Constraints: Shape: Strict circular PCB. Maximum Diameter: 38.5mm (Hard limit). Clearance: Component placement must account for a metallic cylindrical housing. Core Components & Footprints: Microcontroller: Seeed Studio XIAO nRF52840 Sense. Must be surface-mounted (SMD) directly to the carrier board utilizing its castellated holes. RFID ICs: 2x NXP MFRC522. You must use the HVQFN32 (5x5mm) package to meet space constraints. Passives: Include the required 27.12 MHz crystal oscillators and matching circuit arrays for both MFRC522 ICs. Power: 1x JST-PH 2.0mm 2-pin SMD connector. Route this directly to the BAT+ and BAT- pads underneath the XIAO footprint. RF & Antenna Routing Constraints: The board must feature two distinct, integrated PCB trace antennas (one for each MFRC522) operating at 27.12 MHz. Placement: The two antennas must be placed on opposite arcs of the board's outer edge to maximize physical separation and isolate the RF fields for directional sequencing. Tuning: Tuning must account for close proximity to a metallic enclosure (solid steel cylinder). Test Points: Please include exposed SMD test points on the SPI lines (MOSI, MISO, SCK) and the antenna feeds for diagnostic troubleshooting. Wiring Netlist (SPI Bus & Control): The two MFRC522s will share the SPI bus but require isolated Chip Select and Reset lines. Route exactly as follows: Shared SPI: XIAO D8 → SCK on both MFRC522s XIAO D9 → MISO on both MFRC522s XIAO D10 → MOSI on both MFRC522s RFID A Control: XIAO D2 → SDA/CS on RFID A XIAO D3 → RST on RFID A RFID B Control: XIAO D4 → SDA/CS on RFID B XIAO D5 → RST on RFID B Manufacturing Requirements (JLCPCB): The board will be manufactured using the ENIG surface finish. You are responsible for determining the optimal Layer Count (e.g., 2-layer vs. 4-layer) and PCB Thickness (e.g., 1.0mm vs. 1.6mm) required to achieve the correct antenna impedance for your trace design. Required Deliverables: Complete Schematic and Source Files (KiCad, EasyEDA, or Altium). Gerber Files and NC Drill files. JLCPCB-formatted BOM (Bill of Materials) including specific LCSC part numbers for all SMDs. JLCPCB-formatted CPL (Pick & Place / Centroid file). Ordering Checklist: A simple text file explicitly stating the exact Layer Count, PCB Thickness, and Impedance Control settings I need to select on the JLCPCB checkout page so the physical boards match your RF math. Screening Question (Must answer to be considered): How do you plan to handle the impedance matching and antenna tuning to mitigate the metal's interference from the steel cylinder, and do you personally have the necessary equipment (e.g., a VNA) to verify the tuning before generating the gerbers?