RTL Design Engineer — Digital Beamforming Datapath, Custom ASIC (Confidential)

Stealth-mode hardware team building a custom ASIC with a digital beamforming subsystem. Looking for an RTL engineer to own datapath design for the beamforming core. Scope: RTL design (Verilog/SystemVerilog) for the beamforming datapath: per-channel phase/weight application (CORDIC or LUT-based phase rotation, complex multiply-accumulate), multi-channel combining network (systolic/tree-combining architecture), and coefficient update/calibration path Fixed-point pipeline design: quantization strategy, bit-growth management through the MAC/accumulation chain, rounding/saturation logic Clock domain and pipeline balancing across a high-channel-count array (specifics under NDA) Memory/coefficient storage architecture for per-channel weights (double-buffering for dynamic updates) Work from an algorithm-level spec (MATLAB/Python reference model) and produce synthesizable, DFT-clean RTL Support verification: testbench co-design, functional coverage closure, and working with a DV engineer or self-verifying as needed Must have: Deep RTL design experience in Verilog or SystemVerilog for ASIC (not FPGA-only). Synthesis-aware coding, timing closure, DFT/scan awareness Hands-on experience with beamforming, array signal processing, or multi-channel combining logic in hardware i.e. CORDIC-based phase rotation, systolic array architectures, or similar structured datapaths Strong fixed-point design background: bit-width sizing, quantization error analysis, saturation/rounding tradeoffs Comfortable translating a floating-point algorithm reference model into a synthesizable, area/power-optimized RTL implementation Experience with standard ASIC flow: simulation (VCS/Questa/etc.), synthesis (DC/Genus), static timing analysis, basic power estimation Nice to have: Experience with high-channel-count array processing (many parallel MAC datapaths) and associated area/power/timing tradeoffs Low-power design techniques (clock gating, power domains) for datapath-heavy blocks Prior tape-out experience, ideally through GDS handoff Familiarity with UVM or structured verification methodologies Note: Full architecture and system-level specs shared under NDA after initial screening. Please don't ask for system-level or application details in your proposal. We're evaluating RTL/design judgment at this stage. To apply: Briefly describe a fixed-point RTL datapath you've designed (a MAC chain, combining network, CORDIC block, whatever's closest). Walk through your bit-width/quantization decisions and one design tradeoff you had to resolve.