RTL Design & Verification Engineer – ASIC development

We're looking for a digital design and verification engineer to support ASIC development. On the design side, you'll work on RTL with FSM-based control logic, interfacing with analog power/clocking systems, and apply solid fundamentals in CDC, reset strategies, low-power techniques, and timing. On the verification side, you'll build testbenches using SystemVerilog/UVM, constrained random and formal methods, with coverage and debug. Experience with mixed-signal or automotive/high-reliability semiconductor projects is a plus, along with scripting skills (Python/Tcl) for automation. Strong communication and a system-level mindset are essential. In order to apply you must have previous proven working professional experience in ASIC design of digital systems for commercial products (not just University or hobby projects). Please also do not apply if you have only FPGA design experience. We are looking for real hardware digital ASIC designers, not just designers with FPGA/embedded software design/development experience.