RTL/FPGA repository audit, documentation, and provenance review

I’m hiring an experienced RTL/DV or FPGA engineer for a paid Upwork consulting engagement around HDL repository audit, documentation, and provenance review. This is a technical service role. The deliverables are customized written work for my project, such as: - reviewing RTL/DV repository structure and organization - assessing Verilog/SystemVerilog/VHDL codebase layout - checking testbench, simulation, regression, and documentation quality - creating an inventory format for modules, tests, scripts, dependencies, and toolchains - identifying provenance, ownership, dependency, and third-party-IP risk areas - recommending how to package HDL repositories for clean technical handoff - advising on what makes an HDL repository useful for evaluation and benchmarking workflows Strong fits include engineers who have maintained or evaluated private HDL repositories, FPGA reference designs, reusable RTL libraries, UVM environments, formal properties, cocotb tests, protocol blocks, or ASIC/FPGA design flows. The first milestone can be a short consulting session plus a written audit/report structure. I can provide context and representative materials inside the Upwork workroom after a contract is in place. Please only discuss work you are authorized to discuss. Do not share employer, client, or third-party confidential material. Please apply with: 1. Your RTL/DV/FPGA background 2. Repository/toolchain experience 3. Experience with Verilog/SystemVerilog/VHDL, UVM, cocotb, formal, FPGA tools, or ASIC flows 4. Examples of repository types you have worked on, described at a high level 5. How you would structure a first milestone for repository audit/documentation