Senior Altium Engineer Needed for NXP i.MX95 M.2 3042 PCB Design Review

I have a completed compact M.2 3042 secure networking PCB design in Altium and need an experienced hardware/PCB engineer to perform a first-pass Rev A go/no-go risk review before fabrication and assembly. This is not full redesign work yet. The first milestone is a focused engineering triage to identify critical/high-risk issues before I send the board to fab. Any corrections, redesign, or layout fixes will be handled as separate paid follow-on milestones. Project overview: Compact M.2 3042 form factor NXP i.MX95 15×15 application processor LPDDR5, eMMC, PMIC/power tree Wi-Fi/LTE, TPM/eSIM USB, SDIO, UART, SPI 10-layer HDI PCB Altium project, schematic, layout, BOM/AVL, stackup, Gerbers/outputs available Important supply-chain context: Several original BOM parts have become unavailable, long-lead, NRND, restricted, or difficult to source in prototype quantity. Because of this, I am making substitutions for availability before fabrication. The review must verify whether these substitutions are safe electrically, mechanically, and from a software/boot/BSP perspective. Current substitution areas include: Wi-Fi/Bluetooth module change due to Murata lead time LPDDR5 substitution due to stocking/restriction issues eMMC substitution to an available Kingston variant PMIC/power component availability concerns General BOM lifecycle, sourcing, and manufacturability risks Key review areas: Schematic/layout consistency i.MX95 reference design alignment LPDDR5 compatibility, DDR configuration, routing, and boot risk eMMC compatibility and boot/storage risk PMIC/power sequencing and power rail naming Wi-Fi/LTE module integration and RF/antenna risks Impact of Wi-Fi, LPDDR5, eMMC, and other BOM substitutions USB/SDIO/UART/SPI interfaces Clocks, reset, straps, pullups/pulldowns NC/DNC pin handling and unconnected pins 10-layer HDI stackup, BGA/CSP fanout, controlled impedance, length matching DFM/assembly risk Thermal and grounding concerns BOM sourcing/lifecycle risks Must-fix items before fabrication Deliverable: A written block-by-block risk report with: Proceed / do-not-proceed recommendation for Rev A fabrication Critical / High / Medium / Low severity rating for each finding Must-fix before fab / should-fix / Rev B deferral classification Specific recommended changes Rough effort estimate for major fix areas Recommended next milestone scope Acceptance criteria: The report must be specific to the actual Altium project, reference design, and current BOM substitutions. Generic PCB comments will not be accepted. The review should identify critical schematic/layout/BOM risks and provide clear next steps before fabrication. NDA required before files are shared. NXP-related materials may be involved, so contractor must be able to comply with confidentiality and access-control requirements. Please disclose whether you work alone or if any team members/subcontractors would access the files. Initial fixed-price milestone: $300–$400 for first-pass triage review. Follow-on corrections/redesign: separate paid milestones.