Senior Embedded Firmware & Systems Engineer (Real-Time Sensor Fusion & Signal Processing)

Seeking a rigorous, production-grade Senior Embedded Firmware & Systems Engineer to architect a unified C-based sensor library. You will be responsible for building a highly modular, three-layer architecture: a hardware-agnostic Sensor Abstraction Layer (SAL), a Universal DSP pipeline, and a pluggable mathematical backend core. Core Technical Requirements 1. Embedded Architecture & Hard Real-Time Systems Expert proficiency in bare-metal C programming, register-level peripheral optimization (SPI, I2C, UART), and writing deterministic interrupt-driven timing loops. Deep experience with memory-mapped architectures, hardware FIFO ring buffers, and DMA data transfers. Hands-on familiarity with high-performance ARM Cortex cores (specifically platforms like the STM32N6 or ESP32-S3). 2. Applied Numerical Methods & DSP Optimization Numerical Format Discipline: Proven experience writing cross-platform math engines. You must know how to explicitly target platforms with hardware FPUs (float32_t via ARM CMSIS-DSP) as well as resource-constrained, FPU-less platforms (such as the STM32WLE5) requiring native fixed-point integer vector math (q15 or q31). Digital Signal Processing: Expertise in building configurable digital filters, including Biquad topologies (Low-Pass, High-Pass, Notch) and median filters to eliminate environmental and structural noise. 3. Mathematical Foundations (INS & Analytics) Core understanding of state-space kinematics, matrix manipulation, covariance tuning, and Extended Kalman Filtering. Experience with frequency-domain transformation algorithms (FFT/PSD) and mechanical fatigue life estimation models (Rainflow counting, Miner's linear damage rule). Familiarity with non-volatile memory management strategies to safeguard lifecycle telemetry variables against un-signaled power drops. 4. Verification & Testing Standards Experience building PC-based standalone unit test suites to validate embedded code blocks outside of physical target hardware. Proven ability to use synthetic test vectors to profile, characterize, and document numerical error margins between floating-point simulations and fixed-point hardware deployments.