Senior FPGA / DSP Developer: bladeRF 2.0 Continuous 15µs Frequency Hopping & PAL Video

Senior FPGA / DSP Developer: bladeRF 2.0 Continuous 15µs Frequency Hopping & PAL Video Project Description: We are looking for a Senior FPGA / DSP engineer for a highly specialized project on the bladeRF 2.0 micro xA4 platform (Intel Cyclone V, AD9361). The goal is to implement a standalone firmware that generates an analog PAL video signal (static pattern) while continuously hopping between 8 predefined RF frequencies every 15 microseconds. Technical Specifications: Hardware Platform: bladeRF 2.0 micro xA4. Video Standard: PAL (static test pattern generated inside FPGA ROM/RAM). Operation Mode: Standalone (autonomous execution from flash memory without host PC control). RF & Ultra-Fast Hopping Requirements: Operating RF frequency range (LO): 1.0 GHz to 6.0 GHz. Instantaneous bandwidth: 10 MHz. Hopping Mechanism: The system must strictly cycle through 8 different frequency channels, triggering a hop every 15 microseconds continuously. Implementation & Hard Constraints (Critical): Because the hopping interval is exactly 15 µs, standard SPI configuration or Nios II intervention during runtime is impossible due to latency. The developer must program and lock 8 AD9361 Fast Lock Profiles into the transceiver memory during initialization. Real-time frequency switching must be driven entirely by an automated hardware timer inside the FPGA logic, directly toggling the AD9361 control pins (CTRL_IN / Fast Lock Pin Select). The FPGA DSP pipeline must carefully align the continuous PAL I/Q sample generation with the 15µs hopping intervals to manage the phase and PLL settling time of the transceiver. Requirements for the Contractor: Senior-level expertise in VHDL / SystemVerilog and Intel Quartus Prime. Proven track record with advanced AD9361 architecture, specifically: Fast Lock Profiles, SynthLUT calibration, and pin-controlled state machine switching. Strong Digital Signal Processing (DSP) background: mathematical formulation of composite PAL signals into I/Q samples. Expert knowledge of time-domain constraints, clock domain crossing (CDC), and precise hardware timer implementation in FPGA. Mandatory: Access to your own bladeRF 2.0 hardware, along with a high-bandwidth oscilloscope or real-time spectrum analyzer capable of capturing 15µs RF transients for timing verification. Please provide your portfolio regarding high-speed frequency hopping, your estimated timeline, and your fixed price or hourly rate for this scope of work.