Senior Hardware/Firmware Engineer - Ethernet PHY & Switch Debugging

Project Overview We are developing a Partial Discharge (PD) Diagnosis System for High Voltage Substation Monitoring. Current hardware architecture: Zynq SoC ↓ RGMII ↓ Marvell 88E1512 Ethernet PHY ↓ SGMII ↓ Microchip KSZ9477 Ethernet Switch ↓ RJ45 Currently, the SGMII Link between Marvell 88E1512 and KSZ9477 cannot be established. Register configuration, Auto Negotiation, Speed, Duplex, Mode configuration, and MDIO communication have already been verified. We are looking for a senior engineer who can identify the root cause of the SGMII Link failure and recommend either firmware fixes or hardware modifications. (Analysis screenshot attached) Responsibilities Analyze Ethernet PHY initialization SGMII Link Bring-up RGMII Interface MDIO Register Configuration Switch Port Configuration PHY Strap Configuration Clock / Reset Timing Signal Integrity Review FPGA Ethernet configuration Zynq GEM configuration Marvell 88E1512 configuration KSZ9477 configuration Debug PCS Lock Signal Detect Auto Negotiation PRBS SerDes Deliverables Root Cause Analysis Debug Report Firmware Fix Hardware Modification Recommendation Review Meeting Success Bonus & Payment Terms This project is success-based. Compensation will be provided only upon successful completion of the agreed deliverables. USD $500 if the consultant successfully identifies the root cause and provides a validated solution that restores a stable SGMII Link within two weeks from the project start. USD $300 if the same outcome is achieved after two weeks. A "validated solution" means a solution that is reproducible and confirmed by our engineering team, whether through firmware changes, hardware modifications, or a combination of both. No compensation will be provided if the project is discontinued, abandoned by the consultant, or if the agreed deliverables are not completed.