Senior PCB Designer — Large-Format, High-Layer-Count Board (Confidential)

Stealth-mode hardware team building a large, high-complexity PCB. Looking for a senior PCB designer with a track record on genuinely demanding boards (i.e. game console motherboards, server/blade boards, GPU boards, or similarly dense, high-layer-count designs) to own layout for a large single-panel, multi-lamination board. Scope: Layout of large, single-panel (1-up) boards, 14–18 layers, with multiple lamination cycles (sequential/HDI-style build-up as needed) High-speed SERDES routing: length matching, differential pair routing, via/breakout strategy, crosstalk mitigation Long, sensitive analog/RF-adjacent trace routing: controlled impedance, isolation, and coupling management over extended trace lengths Stackup design in collaboration with fab partner: layer assignment, dielectric selection, impedance targets across multiple signal classes Signal integrity considerations throughout: return path management, via stub/backdrill strategy for high-speed layers, isolation between sensitive and noisy domains Power integrity: plane design, decoupling strategy for a board with dense, mixed-signal content DFM/DFA review and coordination with fab/assembly partners given the board's size, layer count, and lamination complexity Reliability considerations: thermal management, via reliability (aspect ratio, plating), material selection for a large, multi-lamination build Must have: Extensive senior-level PCB layout experience on genuinely complex, high-layer-count boards (14+ layers) (e.g., gaming console, server/datacenter, GPU, or similarly dense consumer/enterprise electronics) Direct experience with multiple lamination / sequential build-up processes (not just standard multilayer) Strong high-speed digital layout experience: SERDES routing, differential pairs, length matching, via strategies for multi-Gbps signals Experience routing long, sensitive traces requiring controlled impedance and isolation (RF or high-precision analog) Working knowledge of signal integrity and power integrity principles (not necessarily a dedicated SI/PI engineer, but able to design with SI/PI in mind and collaborate with one) Experience working closely with PCB fabricators on stackup design and DFM for complex boards Proficiency in a professional PCB design tool (Altium, Cadence Allegro, or similar) Nice to have: Experience with boards that combine sensitive analog/RF content and high-speed digital domains on the same design Familiarity with SI/PI simulation tools (or close collaboration history with SI/PI engineers) i.e. HyperLynx, Ansys SIwave, Polar Si9000, etc. Experience with large panel/oversized board manufacturing constraints (panelization limitations, fab size limits, handling/warpage considerations) Reliability/qualification experience (thermal cycling, via reliability testing) for complex multilayer builds Note: Full board specs and application context shared under NDA after initial screening. Please don't ask for application-level details in your proposal. We're evaluating PCB design judgment at this stage. To apply: Briefly describe the most complex board you've laid out (layer count, what made it hard i.e. SERDES routing, stackup, size, whatever's most relevant) and one design decision you're proud of solving.