STM32H723 Minimal Test Board (EasyEDA) — Ethernet PHY + GPIO/SPI Breakout

Project type: internal test/validation board, not a product. Speed and minimal effort matter more than polish, nobody outside our team will ever see this board, so please don't over-engineer it. What we need: Schematic in EasyEDA (required format, if this works out we'll build our future internal boards on top of it). A basic layout is a nice-to-have if you have time, but the schematic is the priority. Base the entire MCU section, power supply, clocking, reset, SWD/debug, directly on the official Nucleo-H723ZG reference schematic. That part is a solved, validated design; please reuse it as-is rather than redesigning anything there. One Ethernet port (RJ45 with integrated magnetics), using the STM32H723's built-in MAC in RMII mode with an external PHY. Break out 8 GPIO and 4 SPI peripherals to clearly labeled headers/pins. No firmware work at all. The only thing that needs verifying is that the chosen SPI pins, the RMII Ethernet pins, and the exposed GPIO don't collide on the same alternate-function assignments. The one part we want done carefully: Ethernet. STM32H7 + RMII has a documented failure mode on ST's own forum/examples: PHYs like the LAN8720 running in REF_CLK_OUT mode (PHY generates the 50MHz clock) don't meet the STM32H7's RMII timing requirements, the PHY's RXD output hold time falls short of what the MCU needs, so the link silently never comes up. That's exactly why the official Nucleo-H723ZG uses a LAN8742A instead. Please use the LAN8742A (or another PHY you can confirm is timing-compatible), and don't generate the 50MHz RMII reference clock from the STM32H7's MCO output, ST also flags that as unsuitable due to jitter. Outside of Ethernet, the rest of the board can be as simple as you like. Why pin choice matters here: if this board works cleanly, it becomes the template for a family of internal boards built around an SPI relay architecture, one side running SPI at 25MHz to read ADCs, forwarding that data out a much faster SPI to an identical downstream board. You don't need to implement any of that now, but please pick the 4 exposed SPI buses/pins with that in mind (peripheral instances/pins that won't fight for routing or AF assignment at higher speed), rather than just grabbing the first 4 free SPI-capable pins. Deliverables: - EasyEDA schematic (shared project) - Pinout/connector table (what's on each header) - One line on the PHY/clock choice and why We're hardware-capable in-house and could do this ourselves, we're outsourcing purely to save time. Ideally looking for someone who's already shipped a working STM32H7 + Ethernet design (please mention if so, and link an example if you can).