10GBASE-T Ethernet Switch Design for RF Shield Room

We’re seeking an experienced Ethernet hardware engineer to develop a commercial 1×1 active regenerative 10G Ethernet interface for an RF-shielded room, with the goal of meeting or exceeding the functionality of comparable active Ethernet penetration products. See https://www.djmelectronics.com/products/activ-10g-ethernet-emi-filter.html and https://hollandshielding.com/en/10-gbit-lan-filter for example products. Project Overview The initial device will have: * One copper RJ45 port on the outside * One copper RJ45 port on the inside * Support for 10M / 100M / 1G / 2.5G / 5G / 10GBASE-T * Independent auto-negotiation on each side * 24 VDC external power * No PoE in the initial version This is not a passive Ethernet feedthrough or transformer-only filter. Each RJ45 link will terminate in its own on-board discrete multi-rate 10GBASE-T PHY. Ethernet traffic will be digitally received by one PHY, pass through an Ethernet switch ASIC, and then be retransmitted through the opposite PHY as a newly generated Ethernet waveform. Conceptually: RJ45 → Magnetics → 10GBASE-T PHY → Ethernet Switch ASIC → 10GBASE-T PHY → Magnetics → RJ45 The intended production design will use discrete on-board PHYs rather than pluggable SFP+ 10GBASE-T modules, allowing us to control magnetics, common-mode filtering, shield bonding, RF layout, thermal management, and enclosure integration. Important objectives include: * Six-speed 10GBASE-T operation * Transparent Ethernet bridging * Independent link negotiation on each side * Very high RF isolation across the shield boundary * Reliable continuous operation * A design architecture that can later support PoE and dual-channel versions Current Architecture Our current preferred switch platform is the Microchip LAN9694, although we’re open to technically superior alternatives. We’d prefer to use a suitable Microchip six-speed 10GBASE-T copper PHY if an appropriate current-production device is available. Otherwise, a device such as the Marvell MV-CUX3610 may be considered. The switch-to-PHY interface is expected to use USXGMII, XFI, or another appropriate high-speed SerDes interface. We already have a preliminary engineering specification describing the proposed architecture, requirements, development stages, and validation approach. Development / Evaluation Board Approach We’re open to using a Microchip LAN969x development/evaluation board, along with appropriate 10GBASE-T PHY evaluation hardware or modules, during an initial architecture and firmware-validation phase. The development platform may be used to prove: * LAN969x switch configuration * PHY-to-switch interoperability * USXGMII/XFI/SerDes operation * Independent auto-negotiation * Operation at different Ethernet rates on each side * Hardware Layer-2 forwarding and buffering * MESA-based initialization and configuration The objective is to reduce technical risk before committing to the custom RF-optimized PCB. Development boards or SFP+ 10GBASE-T modules may be useful during proof-of-concept work, but the intended production unit will use a custom PCB with discrete 10GBASE-T PHYs, Ethernet magnetics, filtering, and chassis/enclosure integration. Primary Engineering Challenge In addition to reliable multi-rate 10G Ethernet operation, the product must provide very high RF isolation across the shield boundary. The design will require careful attention to: * Ethernet magnetics and interwinding capacitance * Common-mode suppression * RJ45 shield-to-chassis bonding * ESD and surge protection * PCB grounding and RF partitioning * High-speed SerDes signal integrity * 24 VDC RF power-entry filtering * Conductive enclosure design * Separation of outside, digital-core, and inside RF sections Experience with EMI/EMC, RF-shielded equipment, shield-wall penetrations, or high-performance RF/conducted filtering is highly desirable. Scope of Work The selected engineer will be expected to: * Review and challenge/refine the proposed architecture * Confirm or recommend the switch ASIC * Identify and recommend the best six-speed 10GBASE-T PHY * Confirm PHY-to-switch interface compatibility * Develop and test an evaluation-board proof of concept where appropriate * Develop detailed schematics and component selection * Design or supervise the high-speed multilayer PCB * Develop the PCB stackup and controlled-impedance requirements * Address SerDes SI, clocks, resets, and power sequencing * Select Ethernet magnetics, CMCs, ESD protection, and related components * Develop the 24 VDC input and RF filtering architecture * Develop minimal firmware required to initialize/configure the switch and PHYs * Configure the device as a simple transparent two-port Layer-2 bridge * Support prototype bring-up and troubleshooting * Develop/support Ethernet performance and RF-isolation testing * Assist with design revisions based on prototype results * Provide complete editable schematics, PCB files, BOM, firmware source, programming instructions, and design documentation The Ethernet data plane should remain in hardware. We’re not looking to develop Ethernet switching software from scratch. If LAN9694 is used, Microchip MESA is expected to provide much of the switch configuration foundation. Required Experience Strong candidates should have hands-on professional experience with: * 10GBASE-T copper Ethernet * External multi-gigabit Ethernet PHYs * Ethernet switch ASICs * USXGMII, XFI, or comparable 10G SerDes * Controlled-impedance multilayer PCB design * High-speed signal integrity * Ethernet magnetics * EMI/EMC design Experience with Microchip/Vitesse Ethernet switches, LAN969x, Microchip MESA, Marvell Alaska PHYs, SI tools such as HyperLynx, RF-shielded equipment, or high-performance EMI filtering would be especially valuable. Please do not apply based primarily on 10/100/1000 Ethernet experience or SFP+/optical 10G experience. We specifically need expertise applicable to 10GBASE-T copper hardware. Proposal Requirements Please identify one or two relevant Ethernet products you personally designed and provide: * Ethernet speed * Switch/MAC part number * PHY/transceiver part number * Copper or optical interface * PHY-to-switch/MAC interface * PCB layer count * Your specific role in schematic design, PCB layout, firmware, and prototype bring-up Please also describe any experience with 10GBASE-T, USXGMII/XFI, Ethernet switch ASICs, EMI/EMC, common-mode filtering, or RF-shielded equipment. We expect to begin with a paid architecture/component-feasibility and development-board proof-of-concept phase before proceeding to the full custom schematic and PCB. Successful completion of the initial 1×1 data-only product may lead to follow-on work developing: 1. 1×1 Ethernet with PoE 2. Dual independent Ethernet channels 3. Dual independent Ethernet channels with PoE