AMD/Xilinx UltraScale+ RTL DSP & Hardware Airlock Demo ($5,000 Fixed - US Persons Only)

Gathol Industries (Wyoming, USA) is seeking an experienced US-based FPGA / RTL Engineer to implement, synthesize, and physically validate a low-latency, register-mapped digital signal processing (DSP) state machine on a commercial AMD/Xilinx FPGA target. The primary objective is to build and demonstrate a universal, passive side-band hardware airlock: proving that raw, high-throughput physical-layer phase variations (ingested via a simulated optical/I/Q stream) can be continuously extracted, verified, and output on-chip independently of an untrusted software/firmware telemetry layer. Target Platform & Hardware Constraints: Target Board: AMD/Xilinx Zynq UltraScale+ MPSoC (Kria KV260 Vision AI Starter Kit or ZCU102 evaluation board). Toolchain & Languages: AMD/Xilinx Vivado Design Suite (v2024.1+), IEEE-compliant standard VHDL or SystemVerilog. System Architecture (Passive Side-Band Model): Path A (Secure Physical DSP Layer): Deterministic, hardware-clocked pipeline that ingests a high-speed I/Q phase vector, executes a fixed-point parallel correlation/extraction algorithm utilizing FPGA DSP slices (DSP48E2 primitives), and routes extracted metrics directly to hardware registers. Path B (Untrusted Software Layer): Simulated software-facing status interface with a register configuration bit allowing an operator to inject arbitrary "spoofed" status states or override software-layer telemetry flags. Isolation Boundary: Path A operates completely decoupled from Path B on a passive side-band tap model. Software-layer manipulations on Path B must have zero physical capability to alter, delay, or inhibit Path A execution. Clocking: Onboard differential system clocks (100 MHz master clock) passing through internal MMCM/PLL primitives to establish synchronous clock domains. Specific Tasks: RTL Architecture Blueprint & Register Map Definition: Define internal FSM managing I/Q data ingest, fixed-point DSP staging, and frame serialization. Document fixed-address register map strictly separating control registers (Path B spoofing toggle) from raw Path A physical-layer diagnostic registers. Fixed-Point DSP Pipeline & Side-Band Ingestion: Construct fixed-point parallel correlation/phase-extraction module using DSP48E2 primitives to ingest golden MATLAB/Python I/Q test vectors provided by Gathol. Dual-Stream Serialization & Visual Hardware Trigger: Serialize and output two simultaneous, synchronized streams via PMOD / I/O header pins: Stream A (Physical Layer): Authentic, un-manipulated DSP phase metrics. Stream B (Telemetry Layer): Software-facing status packet containing injected/manipulated states. Scope Trigger: Drive an onboard high-speed status LED array (and scope trigger pin) directly from Path A logic that instantly flips state the exact microsecond Path A detects a physical phase anomaly, demonstrating deterministic, sub-microsecond hardware latency independently of Path B polling. Explicit Acceptance Criteria (Definition of Done): Criterion 1 (RTL Processing): Compiled RTL pipeline ingests golden I/Q test-vector dataset and correctly computes/outputs fixed-point correlation metric on Path A. Criterion 2 (Data Isolation): Toggling Path B spoofing register manipulates Stream B status telemetry outputs while Stream A physical phase metrics remain 100% un-manipulated, zero-drop, and frame-accurate. Criterion 3 (Physical Hardware Validation): Physical bench demonstration on target hardware showing the onboard LED and scope trigger pin firing instantly on Path A phase anomalies regardless of Path B software spoofing state. Required Qualifications: Must be a U.S. Person (U.S. Citizen or Lawful Permanent Resident / Green Card Holder) physically located in the United States (required for ITAR / EAR export compliance). Direct access to (or ability to acquire) an AMD/Xilinx Kria KV260 Starter Kit (or ZCU102) and basic bench measurement equipment (oscilloscope or logic analyzer). Deep proficiency in VHDL / SystemVerilog, Vivado Design Suite, MMCM/PLL clock primitives, and DSP48E2 slice instantiation. Demonstrated experience with hardware-in-the-loop (HIL) synthesis, bitstream flashing, and physical pin timing verification. Engagement Terms ($5,000 USD Fixed-Fee): Contracting Entity: Gathol Industries, Inc. (Wyoming, USA). Milestone 1 ($1,000 / 20%): Architecture Blueprint & Register Specification Execution of NDA/IP assignment, repository access, delivery of FSM state transition diagrams, fixed-address register map, and top-level RTL structural schema showing physical decoupling between Path A and Path B. Milestone 2 ($2,000 / 40%): RTL Core & Cycle-Accurate Simulation Synthesizable VHDL/SystemVerilog source files and Vivado testbench environment demonstrating behavioral verification of the DSP ingestion pipeline under test-vector feeds. Milestone 3 ($2,000 / 40%): Hardware Synthesis, Bench Demo & Final Delivery Fully synthesized, timing-closed Vivado project, compiled bitstream (.bit/.bin) flashed onto target hardware, live bench demonstration fulfilling all three Acceptance Criteria, and concise technical report covering resource utilization (LUTs, DSP slices, BRAM) and timing closure metrics.