SystemVerilog/UVM testbench and HDL repository audit

Posted 3 weeks ago

Worldwide

Summary

I’m hiring an experienced digital verification / RTL engineer for a paid Upwork consulting engagement focused on HDL repository audit, testbench quality, and verification documentation. This is a technical service role. I’m looking for someone who can review or help define what a high-quality HDL repository should contain for evaluation and handoff workflows. Relevant deliverables may include: - reviewing SystemVerilog/Verilog/VHDL repository structure - assessing testbench organization, UVM/cocotb environments, assertions, and formal properties - checking simulation/regression scripts, Makefiles, CI setup, coverage artifacts, and waveform/debug workflows - creating an inventory format for modules, interfaces, tests, scripts, dependencies, and toolchains - evaluating documentation quality: README, architecture notes, block specs, register maps, interfaces, setup instructions, and expected outputs - identifying provenance, third-party dependency, and ownership risk areas - recommending how to package HDL repositories so another engineer can reproduce simulations and understand design intent Strong fits include engineers who have maintained serious Git/GitHub/GitLab HDL repositories with documented RTL, testbenches, simulator setup, regression history, and bug-fix history. Experience with SystemVerilog, UVM, cocotb, Verilator, Icarus, ModelSim/Questa, Vivado, Quartus, SymbiYosys, or formal tools is especially relevant. The first milestone can be a short consulting session plus a written audit template/checklist for HDL repositories and verification assets. Please only discuss work you are authorized to discuss. Do not share employer, client, or third-party confidential material. Please apply with: 1. Your RTL/DV background 2. Your experience with SystemVerilog, Verilog, VHDL, UVM, cocotb, assertions, formal, or simulation regressions 3. Examples of HDL repository types you have maintained or reviewed, described at a high level 4. What you think a well-packaged HDL repo should include: docs, tests, scripts, CI, tool versions, coverage, waveforms, etc. 5. How you would structure a first audit/documentation milestone

  • Less than 30 hrs/week
    Hourly
  • < 1 month
    Duration
  • Expert
    Experience Level
  • $50.00

    -

    $150.00

    Hourly
  • Remote Job
  • One-time project
    Project Type
Skills and Expertise
Mandatory skills
SystemVerilog
Verilog
Activity on this job
  • Proposals:15 to 20
  • Interviewing:
    4
  • Invites sent:
    30
  • Unanswered invites:
    19
About the client
Member since Jun 28, 2020
  • United States
    6:38 AM
  • Mid-sized company (10-99 people)

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