Hire the Best VHDL Specialists
in Bangladesh

With 7 years of hands-on experience in FPGA/RTL front-end design, IP-level functional verification, and SoC design closure, I deliver production-ready silicon with a consistent record of coverage closure across complex protocols — PCIe Gen3/4/5, AXI4, AXI4-Stream, AHB, APB, and QSPI. --- RTL DESIGN & SoC FRONT-END --- I lead end-to-end SoC front-end design flows: micro-architecture definition, RTL coding (Verilog, SystemVerilog, VHDL), RTL integration, synthesis, static timing analysis (STA), clock domain crossing (CDC), linting, power optimization, and manufacturing-ready database delivery. Tools: Xilinx Vivado, Synopsys Design Compiler, PrimeTime. --- FUNCTIONAL VERIFICATION (UVM / CoCoTB / SVA) --- Expert in building and architecting UVM testbenches from scratch — scoreboard, coverage collector, register abstraction layer (RAL), sequence libraries, and virtual sequencers. Skilled in SystemVerilog Assertions (SVA), constraint-random verification, error injection, and corner-case simulation at block and chip level. I also build Python-based CoCoTB environments for modern RTL flows. Simulators: Cadence Xcelium, Synopsys VCS, ModelSim/Questa. --- FORMAL VERIFICATION & ADVANCED FLOWS --- Hands-on with formal property verification, CDC analysis, X-propagation, power intent (UPF), and structural linting. Experienced with ARM Cortex-M/A and RISC-V SoC verification including subsystem integration and full-chip closure sign-off. --- PROTOCOLS --- - PCIe Gen3/4/5 (TLP, DLLP, Physical Layer) - AXI4, AXI4-Lite, AXI4-Stream - AHB, APB (AMBA suite) - QSPI XIP Controller - 5G datapath (AXI4-Stream based) --- TEAM LEADERSHIP & PROJECT DELIVERY --- Proven team lead directing RTL and verification engineers on: - PCIe Gen5 controller RTL design & UVM verification - AXI4-Stream 5G datapath block & chip-level verification - QSPI XIP controller design & verification - AMBA protocol IP verification (AXI4/AHB/APB) --- CORE SKILLS & TOOLS --- Languages: Verilog | SystemVerilog | VHDL | Python | TCL Verification: UVM | CoCoTB | SVA | RAL | Functional Coverage Simulators: Cadence Xcelium | Synopsys VCS | ModelSim/Questa Synthesis/STA: Xilinx Vivado | Synopsys Design Compiler | PrimeTime Protocols: PCIe Gen5 | AXI4 | AHB | APB | QSPI Formal: Cadence JasperGold | Synopsys VC Formal --- WHAT CLIENTS SAY I DELIVER --- - Clean, well-commented, synthesizable RTL code - Reusable, scalable UVM environments with full coverage closure - Detailed verification plans, test plans, and coverage reports - On-time delivery with clear communication at every milestone - Post-silicon debug support and waveform analysis --- INDUSTRIES & APPLICATIONS --- Semiconductor IP design, data center interconnects (PCIe), wireless baseband (5G NR), automotive SoC, embedded FPGA prototyping, RISC-V custom processor design, memory controller verification, and industrial IoT. --- WHY HIRE ME --- I combine deep protocol expertise with silicon-proven methodologies. Whether you are taping out a new chip, verifying a complex IP block, or building a custom FPGA solution, I apply the same rigour used at leading semiconductor companies — adapted to your timeline and budget. Need a robust UVM testbench, RTL design from spec, formal verification, SoC integration, or front-end project leadership? I bring the technical depth and delivery discipline to get it done right, on time. Let's build reliable silicon together.

My name is Ruhul Amin. I am presently employed as a Senior embedded engineer and Tech Lead at BJIT Ltd. Software Company. Throughout my career, I have undertaken various projects involving microcontrollers, microprocessors, SoCs, and more. With a focus on embedded systems, I’m a software engineer. Thanks to my passion and hard work, throughout of my career I’ve developed a strong foundation in Embedded, IoT, FPGA, DSP, Machine Learning, and Desktop Applications. With years of expertise, quick learning and analytic skills, and an enthusiasm for new technologies and challenges, I can provide the best system architectural design and efficient market implementation in a short amount of time. Specialized Skills: C, C++, Python, Verilog, Arduino, ESP32, STM32, nRF52, MSP430, ARM, FPGA, DSP, SoC, RTOS, Embedded Linux, Yocto, UART, SPI, I2C, CAN2.0B, Bluetooth, IoT, MQTT, TCP-IP, Wireshark, Audio-Video Signal Processing, Xilinx ISE, Code Composer Studio, Visual Studio, Oscilloscope, Git, Jira, Confluence, etc.

I develop embedded electronic systems that combine Digital Signal Processing, power electronics, circuit and PCB design, firmware, motor control, and machine learning—from low-frequency audio and vibration analysis, digital filters, FFT, feature extraction, and pattern recognition to inverters, converters, motor drivers, and real-time microcontroller implementation. My expertise includes: • Embedded systems development using STM32, ESP32, AVR, nRF52, and Arduino-compatible platforms • Low-frequency audio and vibration signal processing • IIR/FIR digital filter design, FFT analysis, cross-correlation, feature extraction, and noise reduction • Pattern recognition, anomaly detection, condition monitoring, and predictive maintenance • Machine-learning model development using neural networks and support vector machines • Power electronics, including inverters, DC-DC converters, battery and supercapacitor chargers, and BMS • BLDC, stepper, servo, and closed-loop motor-control systems • Analog circuit design, sensor interfacing, data acquisition, schematic design, and PCB layout I focus on delivering reliable, practical, and manufacturable solutions with clear communication and thorough documentation.