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Design and implement a convolution encoder used in IEEE802.11 or IEEE802.16 standards. Requirements/Tasks: 1. From the specification of the convolutional encoder, Polynomial or Octal number, in the standards, derive the circuit and select required components. Justify your decision. Build the Simulink model to prove the functional design. Justify how your design meets the requirement. 2. Design the selected Convolution Encoder using model-based design methodology, System Generator for DSP, to further verify the Convolution Encoder. Justify your design. Implement your design on FPGA hardware. Verify the design via Hardware in the loop method. 3. Synthesis the design using Xilinx Vivado design tool and analyse/discuss the resources used and speed impact. Evaluate its performance including the environmental and societal impact. Identify the critical path in your design. Discuss the potential techniques which can be used to improve the design to meet the requirement and it’s the drawback, if the speed did not meet the requirement. 4. Write VHDL code to implement the Convolutional encoder. Use the same binary input from Simulink and compare the results with that obtained in the model-based design.

I need someone to help me with Create an Asteroids style game using VHDL, i will share more details in the chat.

Looking for an experienced FPGA engineer to design an AXI Stream hardware accelerator for the first convolutional layer of LeNet CNN. The goal is to speed up handwritten digit recognition on the PYNQ Z2 platform. Deliverables include Vivado project files, overlay files (.bit, .hwh, .tcl), and a short report. Must have expertise in FPGA design, Xilinx Vivado, and CNN architectures. Let me know your approach and relevant experience!

We are currently in the implementation phase of the hardware that will be used to control a three-phase open-winding PMSM. The printed circuit board (pcb) is currently being built and we anticipate its arrival in the next few weeks. The microcontroller that has been selected is TMS320F28379D from Texas instruments and the pin mapping for I/Os have been documented and integrated in the design of the pcb. We have a three-phase open-winding PMSM rated at 2HP and has 24 pole pairs. The maximum speed of the PMSM is 3000 rpm. The PMSM will be connected to the medium voltage output terminals on the pcb. An incremental encoder has been fitted to the shaft of the PMSM and is capable of 16,384 counts per revolution in full quadrature mode. We are currently looking for expert help to implement the firmware using the Code Composer Studio from Texas Instruments. The selected firmware will be divided into four primary modules as follows: 1. Mechanical Speed and Angle monitoring module, 2. Sinusoidal PWM Conversion module, 3. The Motor Controller Module, 4. Fault Protection module. The inputs to pcb are: 1. Motor ON/OFF two-position normally open switch, 2. Motor Emergency Stop two-position normally closed switch, 3. Motor Forward/Reverse two-position normally open switch, 4. MCU external reset momentary two-position normally closed switch, 5. Shaft mounted Incremental Encoder with A, B and index signals, 6. Speed Setpoint dial with integrated incremental encoder (A,B signals), 7. Three-phase stator currents, 8. DC Bus voltage, 9. DC input current, The output signals are: 1. SPWM signals to three Mosfet H-bridge modules, 2. Fault signal to halt triggering of all Mosfets to protect against: a. Short-circuits and, b. Over and under voltages at the DC bus. 3. Trigger signal to engage and disengage the pre-charge circuit. The derived signals are: 1. Motor mechanical speed (rad/s and RPM), 2. Motor mechanical angle (rad and degrees), 3. Direct and quadrature axis voltages, 4. Direct and quadrature axis currents, 5. Motor input electrical power. Motor incremental encoder calibration map: Note that the shaft incremental encoder will be calibrated to ensure alignment with the intrinsic angular displacement of the motor. As the offset is expected to be nonlinear, a calibration map will be provided with several breakpoints of actual encoder count (relative to the encoder home position) versus calibrated mechanical angle relative to the intrinsic zero degree position. This should be programmable in the firmware. Firmware in Code Composer Studio: The firmware should consider the above stated and must be testable in a recent version of the Code Composer Studio. The firmware shall have the means to simulate the motor’s incremental encoder ABZ signals to demonstrate speed and angle calculations at speeds up to 3000 rpm. The firmware shall also have the means to calculate the motor speed and angle with the ABZ signals from the motor’s actual incremental encoder. We expect that all signals will be demonstrable using the variable watch feature of the Code Composer Studio. The firmware shall be properly documented with adequate submodules for easy readability. The firmware for the Mechanical Speed and Angle monitoring module shall be developed to consider a minimum speed of 10 rpm and maximum speed of 3000 rpm. If filtering is required for the speed output, it shall be based on the Kalman Filtering algorithm. The Mechanical Speed and Angle monitoring module shall operate at a rate of 20 kHz (operator tuneable). The firmware for the Sinusoidal PWM Conversion module shall be based on algorithm that will be provided by us in MATLAB function format. This module will be composed of a ‘Inverse Parke’ function and a three-phase to SPWM conversion function. Appropriate ePWM modules shall be written based on the outputs from the three-phase to SPWM conversion function. The Sinusoidal PWM Conversion module shall operate at a rate of 20 kHz (operator tuneable). The firmware for the Motor Controller Module is proprietary and only the truncated version of the MATLAB functions will be provided, that is, without the details. However, all the constants and variables used by the functions of the Motor Controller Module will be supplied by us. The Motor Controller Module shall operate at a rate of 200 Hz (operator tuneable). The firmware for the Fault Protection module shall be developed based the requirement provided by us to protect against short-circuits and over and under voltages at the DC bus. It shall also consider the condition required to engage and disengage the pre-charge circuit. The detailed logic will be provided by us based on the required protection. The Fault Protection module shall operate at a rate of 20 kHz (operator tuneable). Fixed price quote Candidates should provide a fixed-price quote based on the outlined scope of work. The firmware must be developed in Code Composer Studio and demonstrate the effectiveness of the implementation using the software’s debugging and variable watch features. The firmware should be well-commented and include proper documentation for each module to ensure readability and maintainability. The implementation should be efficient and reliable, with particular attention to the real-time aspects of controlling the motor and ensuring safe operation.

Looking for an experienced FPGA engineer to design an AXI Stream hardware accelerator for the first convolutional layer of LeNet CNN. The goal is to speed up handwritten digit recognition on the PYNQ Z2 platform. Deliverables include Vivado project files, overlay files (.bit, .hwh, .tcl), and a short report. Must have expertise in FPGA design, Xilinx Vivado, and CNN architectures. Let me know your approach and relevant experience!

We are seeking an experienced VHDL developer to assist in the integration of an Arithmetic Logic Unit (ALU) into a RISC chip architecture. The ideal candidate will have a strong background in digital design and VHDL coding. Responsibilities include designing, simulating, and testing the ALU functionality within the RISC framework. A thorough understanding of RISC architecture and previous experience with hardware description languages is essential. If you have a passion for embedded systems and chip design, we would love to hear from you!

I need someone who can design an ASIC circuit using verilog or VHDL for ARINC 429 inputs/outputs and ARINC 708 inputs/outputs.

We are seeking a freelance engineer to resolve Compass (AK09918) and IMU calibration issues in our automotive HMI device (PCID). The sensors display inaccurate and erratic data inside the vehicle. Tasks include diagnosing the issue, developing calibration procedures, and optimizing performance in a Linux Kernel 5.10 and Incari Yocto environment. The project must address hard/soft iron distortion and IMU drift, with practical testing required for validation. Deliverables include a root cause analysis, calibration methods, testing results, and detailed documentation. The timeline for completion is 2 to 3 weeks. Experience with automotive-grade sensors, Yocto-based environments, and embedded systems is essential.

Hardware Design Developer - Verilog Jupiter AI LABS is searching for an exceptional hardware design Developer to play a pivotal role in using the hardware design platform to generate the training data to enhance enterprise LLMs' capabilities. This unique position offers the chance to directly contribute to the sophistication of enterprise LLMs, ensuring they operate with unparalleled efficiency and intelligence. Your Mission: Develop, configure, and customize the hardware design platform, utilizing it to generate vital training data for enterprise LLMs. Liaise with research teams to translate requirements into actionable data insights, directly impacting our LLMs' performance. Uphold the highest standards in coding, debugging, and documentation, ensuring the hardware design solutions are optimized for LLM training and benchmarking. Collaborate across teams to identify and prioritize needs, contributing to the LLMs' ability to understand and automate complex processes. Job Requirements: BS or MS degree in Electrical, Engineering, or related field. 3-5 years of proven experience in hardware design development. Expertise in HDLs such as Verilog, SystemVerilog, VHDL, and SystemC. Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment. Exceptional problem-solving, communication, and collaborative skills. Familiarity with Synopsys/Cadence or open source toolchains Plus, if You Have Expertise in UVM environments Expertise in Formal Verification Expertise in Lint process and refinement Experience with Computer Architecture and Assembly Coding and Debugging Experience with Assertion Coding and SVA Familiarity with ML and AI systems Search Guidance Paid interview of 90 min Hourly rate: $6- 8 USD or monthly pay - USD 1280 Are you available from fixed pay of $1280 for one month cycle. If yes the payment will be in this way, if you work from 1nov to 30 nov , our system pay by 15-18 dec as per upwork payment , and similar the cycle continue every month. Total Years Of exp- 3+ years Mandatory Opportunity- Full Time Contract, 8 hours Notice Period:Immediate Mandatory Skills: Min of 2 years of relevant experience. Hardware Design and/or Hardware Verification Experience with one or more on the list below ASIC VLSI FPGA SOC Experience with one more on the list below SystemVerilog development Verilog development Testbench development and/or verification. Key Experiences: IP Development - Verification and Front End. Development - EDA Tools ( VLSI Industry) Verilog + System Verilog Look for Project Description Including: Type of Modules - Described in projects that he implemented and integrated. Engaged in IP, USP,HDM. Can solve problems and not just connect in the system. Able to describe and develop test plan Verification workflow - implementation , Checker System, Test Strategy, Should be able to provide indication, optimization, Verification to Front End Teams. They should know what is IP and should be able to solve IP problems. Look for profiles describing projects integrated in systems, engaging IPs,development of IP Pre-screening - mandatory questions: What is your experience with HDLs and scripts? Which ones are you familiar with, and for which applications? Have you made design improvements (area, timing, performance, capability) in an existent IP (e.g., adders, DSPs, processor, etc.)? If so, tell me why and how you had to improve it. Have you worked on improving a project's verification lead time? What was your approach and what were the results? How does the compressed instruction set (RV32C) enhance the performance and efficiency of RISC-V systems? Have you utilized any open-source LLM (Large Language Models) for convenience in your daily workflows? If so, which ones? On this job, you won't be working building a project but training an LLM.

Technology stack: 1. Teensy 4.0 with the FlexCAN_T4 library 2. Processing 4.1.2 (Java-like) language Task: Fix the corrupted data issue in a bidirectional serial-port (UART) communication. Both Teensy and Processing should receive unshifted data. Envisioned solution: - 2 threads on Teensy: one for Serial Tx in the main loop, another one for Serial Rx in a second loop, e.g. yield(), serialEvent(), or TeensyThread. - synchronization between Teensy and Processing Tx buffers: either hardware (RTS/CTS pins of UART) or software (XON/XOF or a lightweight custom protocol with acknowlendgements) Current use case: Teensy and Processing exchange serial data asynchronously. Teensy constantly sends a burst of data to Processing. This burst of data is received from CAN on interrupts. Processing periodically sends data to Teensy. Issue: Teensy always receives correct data from Processing. However, when a collision between Tx on Teensy and Tx on Processing occurs, the data from Teensy gets shifted, and is received shifted by Processing. If no data is sent from Processing to Teensy, Processing always receives correct data. Example code: I attach a simplified (with no CAN data) Teensy code which recreates the issue. Deliverables: A Teensy code capable of receiving correct Serial data and transmitting correct Serial data via the same port. The incoming Serial data can appear randomly. The transmitted Serial data should be generated and sent out on interrupts.