Hire the Best Digital Signal Processing Specialists
in Bangladesh

I am a Machine Learning Engineer with four years of experience working across deep learning research, large scale AI systems, and production model deployment. Over the years, I have worked extensively in medical imaging, computer vision, NLP, signal processing, and large language models, building systems that range from experimental research pipelines to deployed real world AI applications. My day to day work primarily involves Python, PyTorch, TensorFlow, Keras, HuggingFace Transformers, sentence transformers, scikit learn, OpenCV, Pandas, and NumPy. I enjoy working deeply on both the research and engineering sides of machine learning, especially problems that require understanding model behavior rather than simply applying existing architectures blindly. A large part of my background is research driven. I have authored multiple peer reviewed publications in indexed journals and IEEE conferences, including publications in Neurocomputing, Healthcare Analytics, Engineering Applications of Artificial Intelligence, Telematics and Informatics Reports, and other Elsevier and IEEE venues. My research has focused heavily on explainable AI, healthcare AI, and advanced deep learning systems. Some of my published work includes CARDxnosis, an explainable knowledge driven framework for ECG diagnosis and clinical report generation, an explainable AI system for trustworthy arrhythmia detection, a CNN RNN Attention hybrid architecture for automatic modulation classification, ensemble deep learning approaches for lung cancer detection from CT scans, and SRGAN based white blood cell image generation and classification pipelines. Alongside published work, I am currently involved in research on brain tumor segmentation, ADHD and ASD classification from brain connectome graphs, epileptic seizure prediction from EEG signals, and interpretable tabular learning using graph neural networks combined with Kolmogorov Arnold Networks. Beyond research, I have substantial hands on experience building and deploying production grade AI systems. One of my major recent projects was LaborBERT v4, a domain adaptive transformer fine tuning system processing hundreds of thousands of records through a large scale training pipeline. The project involved multiple experimental setups including contrastive learning, masked language model pretraining, temporal contrastive learning, cross attention based fusion, multi task training, and Matryoshka Representation Learning. I have also built hybrid embeddings plus LLM systems for taxonomy mapping using OpenAI embeddings alongside locally hosted LLaMA and Mistral models through Ollama. In addition, I have worked on deployed clinical AI systems and a portable on device diagnostic AI solution with embedded deep learning models for point of care inference, which gave me valuable experience in optimization, deployment constraints, inference design, and production reliability. My broader project portfolio includes vehicle detection using Mask R CNN, human activity recognition on the Kinetics 700 dataset, facial keypoint detection with MultiRes UNet, semantic segmentation pipeline redesign, Stable Diffusion based image editing workflows, toxic comment classification, RASA based conversational AI systems, and large scale scraping and automation pipelines using Playwright and Selenium. I have also worked with Flask and Django based deployment pipelines and cloud hosted ML systems. From an engineering perspective, I care strongly about clean and maintainable systems. I follow disciplined workflows involving modular code design, Git based version control, reproducible experimentation, structured evaluation, bootstrap validated metrics, and detailed documentation. I am also comfortable preparing scientific reports, research papers, and journal submissions using both LaTeX and Word. What ties all of this together is that I genuinely enjoy solving difficult technical problems, especially the kind that require balancing research depth with practical engineering constraints. I am most motivated by projects where thoughtful experimentation, careful system design, and real world usability matter equally.

Presently pursuing my M.Sc. degree in Biomedical Engineering at Bangladesh University of Engineering and Technology, Bangladesh. I am currently working on biomedical signal processing and deep learning-based health informatics projects as an active member of the m-health lab. My other research interests include biomedical simulations, biomedical Instrumentation, and edge device optimization. I am pretty much proficient in python and Matlab programming.

I develop embedded electronic systems that combine Digital Signal Processing, power electronics, circuit and PCB design, firmware, motor control, and machine learning—from low-frequency audio and vibration analysis, digital filters, FFT, feature extraction, and pattern recognition to inverters, converters, motor drivers, and real-time microcontroller implementation. My expertise includes: • Embedded systems development using STM32, ESP32, AVR, nRF52, and Arduino-compatible platforms • Low-frequency audio and vibration signal processing • IIR/FIR digital filter design, FFT analysis, cross-correlation, feature extraction, and noise reduction • Pattern recognition, anomaly detection, condition monitoring, and predictive maintenance • Machine-learning model development using neural networks and support vector machines • Power electronics, including inverters, DC-DC converters, battery and supercapacitor chargers, and BMS • BLDC, stepper, servo, and closed-loop motor-control systems • Analog circuit design, sensor interfacing, data acquisition, schematic design, and PCB layout I focus on delivering reliable, practical, and manufacturable solutions with clear communication and thorough documentation.

My name is Ruhul Amin. I am presently employed as a Senior embedded engineer and Tech Lead at BJIT Ltd. Software Company. Throughout my career, I have undertaken various projects involving microcontrollers, microprocessors, SoCs, and more. With a focus on embedded systems, I’m a software engineer. Thanks to my passion and hard work, throughout of my career I’ve developed a strong foundation in Embedded, IoT, FPGA, DSP, Machine Learning, and Desktop Applications. With years of expertise, quick learning and analytic skills, and an enthusiasm for new technologies and challenges, I can provide the best system architectural design and efficient market implementation in a short amount of time. Specialized Skills: C, C++, Python, Verilog, Arduino, ESP32, STM32, nRF52, MSP430, ARM, FPGA, DSP, SoC, RTOS, Embedded Linux, Yocto, UART, SPI, I2C, CAN2.0B, Bluetooth, IoT, MQTT, TCP-IP, Wireshark, Audio-Video Signal Processing, Xilinx ISE, Code Composer Studio, Visual Studio, Oscilloscope, Git, Jira, Confluence, etc.

With 7 years of hands-on experience in FPGA/RTL front-end design, IP-level functional verification, and SoC design closure, I deliver production-ready silicon with a consistent record of coverage closure across complex protocols — PCIe Gen3/4/5, AXI4, AXI4-Stream, AHB, APB, and QSPI. --- RTL DESIGN & SoC FRONT-END --- I lead end-to-end SoC front-end design flows: micro-architecture definition, RTL coding (Verilog, SystemVerilog, VHDL), RTL integration, synthesis, static timing analysis (STA), clock domain crossing (CDC), linting, power optimization, and manufacturing-ready database delivery. Tools: Xilinx Vivado, Synopsys Design Compiler, PrimeTime. --- FUNCTIONAL VERIFICATION (UVM / CoCoTB / SVA) --- Expert in building and architecting UVM testbenches from scratch — scoreboard, coverage collector, register abstraction layer (RAL), sequence libraries, and virtual sequencers. Skilled in SystemVerilog Assertions (SVA), constraint-random verification, error injection, and corner-case simulation at block and chip level. I also build Python-based CoCoTB environments for modern RTL flows. Simulators: Cadence Xcelium, Synopsys VCS, ModelSim/Questa. --- FORMAL VERIFICATION & ADVANCED FLOWS --- Hands-on with formal property verification, CDC analysis, X-propagation, power intent (UPF), and structural linting. Experienced with ARM Cortex-M/A and RISC-V SoC verification including subsystem integration and full-chip closure sign-off. --- PROTOCOLS --- - PCIe Gen3/4/5 (TLP, DLLP, Physical Layer) - AXI4, AXI4-Lite, AXI4-Stream - AHB, APB (AMBA suite) - QSPI XIP Controller - 5G datapath (AXI4-Stream based) --- TEAM LEADERSHIP & PROJECT DELIVERY --- Proven team lead directing RTL and verification engineers on: - PCIe Gen5 controller RTL design & UVM verification - AXI4-Stream 5G datapath block & chip-level verification - QSPI XIP controller design & verification - AMBA protocol IP verification (AXI4/AHB/APB) --- CORE SKILLS & TOOLS --- Languages: Verilog | SystemVerilog | VHDL | Python | TCL Verification: UVM | CoCoTB | SVA | RAL | Functional Coverage Simulators: Cadence Xcelium | Synopsys VCS | ModelSim/Questa Synthesis/STA: Xilinx Vivado | Synopsys Design Compiler | PrimeTime Protocols: PCIe Gen5 | AXI4 | AHB | APB | QSPI Formal: Cadence JasperGold | Synopsys VC Formal --- WHAT CLIENTS SAY I DELIVER --- - Clean, well-commented, synthesizable RTL code - Reusable, scalable UVM environments with full coverage closure - Detailed verification plans, test plans, and coverage reports - On-time delivery with clear communication at every milestone - Post-silicon debug support and waveform analysis --- INDUSTRIES & APPLICATIONS --- Semiconductor IP design, data center interconnects (PCIe), wireless baseband (5G NR), automotive SoC, embedded FPGA prototyping, RISC-V custom processor design, memory controller verification, and industrial IoT. --- WHY HIRE ME --- I combine deep protocol expertise with silicon-proven methodologies. Whether you are taping out a new chip, verifying a complex IP block, or building a custom FPGA solution, I apply the same rigour used at leading semiconductor companies — adapted to your timeline and budget. Need a robust UVM testbench, RTL design from spec, formal verification, SoC integration, or front-end project leadership? I bring the technical depth and delivery discipline to get it done right, on time. Let's build reliable silicon together.

Hi there! I'm Sabbir Mahamud, a Biomedical Engineering graduate from Jashore University of Science and Technology, with a strong passion for leveraging technology to improve human health. My expertise lies in signal processing, machine learning model development, and real-time device integration.