You will get I will design power electronics and control systems in MATLAB Simulink
Project details
You'll receive a design backed by stability analysis not a model that happens to settle on screen.
The common failure in converter and control work is a loop that simulates fine but oscillates or overshoots in hardware, because the compensator was tuned by hand with no idea of the actual phase margin. I design in the frequency domain: derive the plant model, shape the loop to an explicit crossover frequency and phase margin, then verify on both averaged and switched models so you can see the real ripple and transient behaviour.
I'm an electronics engineer with 10+ years of experience across power electronics, control systems, FPGA, and DSP, with prior industry experience as a design engineer. That range means I can also take the control loop into digital implementation if you need it on a microcontroller or FPGA.
You'll get commented MATLAB and Simulink files, the full result set Bode plots, step responses, stability margins, ripple and transient waveforms and a report explaining every design decision.
Message me before ordering with your specifications and I'll confirm the approach and timeline.
The common failure in converter and control work is a loop that simulates fine but oscillates or overshoots in hardware, because the compensator was tuned by hand with no idea of the actual phase margin. I design in the frequency domain: derive the plant model, shape the loop to an explicit crossover frequency and phase margin, then verify on both averaged and switched models so you can see the real ripple and transient behaviour.
I'm an electronics engineer with 10+ years of experience across power electronics, control systems, FPGA, and DSP, with prior industry experience as a design engineer. That range means I can also take the control loop into digital implementation if you need it on a microcontroller or FPGA.
You'll get commented MATLAB and Simulink files, the full result set Bode plots, step responses, stability margins, ripple and transient waveforms and a report explaining every design decision.
Message me before ordering with your specifications and I'll confirm the approach and timeline.
AI Development Type
Model Tuning, Recommendation SystemAI Tools
MATLAB, PyTorchAI Development Language
PythonWhat's included
| Service Tiers |
Starter
$100
|
Standard
$260
|
Advanced
$560
|
|---|---|---|---|
| Delivery Time | 3 days | 6 days | 15 days |
Number of Revisions | 1 | 2 | 3 |
AI Model Integration | - | - | |
Detailed Code Comments | |||
Knowledge Graph | - | - | |
Model Documentation | - | ||
Ontology | - | - | |
Source Code | |||
Taxonomy | - |
Frequently asked questions
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About Abdul
FPGA & Signal Processing Engineer | Verilog, Vitis HLS, MATLAB Expert
Malakand, Pakistan - 12:46 pm local time
I take projects end to end: from initial MATLAB modeling through Verilog RTL and Vitis HLS to full hardware deployment on Xilinx Zynq, Kria KV260 and KR260 platforms.
What I can do for you:
✅ FPGA / RTL design in Verilog, SystemVerilog and VHDL
✅ Vitis HLS, converting C/C++ algorithms into optimized hardware IP
✅ Signal processing accelerators (FFT, IFFT, FIR, matrix operations, custom DSP cores)
✅ AI / vision acceleration on Kria KV260 and KR260 (DPU, Vitis AI, smart-camera and robotics pipelines)
✅ MATLAB / Simulink modeling, fixed-point conversion, and golden-reference verification
✅ Vivado design flow: IP integration, AXI4 / AXI-Stream interfaces, synthesis, timing closure
✅ Zynq SoC and Kria hardware-software co-design (PYNQ, PetaLinux, bare-metal)
✅ Testbench development, simulation, and waveform debugging (ModelSim, Vivado XSIM)
✅ PCB design support for FPGA / SoC boards
Background:
• Master's research in FPGA design, currently developing a Serial Commutator FFT (SC-FFT) accelerator for millimeter-wave SAR imaging on the Xilinx Zynq-7020
• Former SoC Design Engineer at the National Institute of Electronics (Pakistan), full-cycle digital and FPGA design
• Bachelor's in Electrical and Electronic Engineering, Air University, Islamabad
• Active researcher in FPGA-based AI and DSP acceleration
Tools & technologies:
Verilog, SystemVerilog, VHDL, Vitis HLS, Vivado, Vitis/Xilinx SDK, Vitis AI, MATLAB, Simulink, Python (PYNQ), C/C++, PetaLinux, Git, Altium Designer, KiCad
Platforms: Zynq-7000, Zynq UltraScale+, Kria KV260 & KR260, Artix-7
Why clients work with me:
✅ Verification-first approach, every module is simulated and tested before integration
✅ Clean, well-commented code with proper documentation
✅ Clear, on-time communication with updates at every stage
✅ Realistic timelines and honest scope, no overpromising
Whether it's a single RTL module or a full FPGA system, send me your requirements. I'll review them and come back with a clear plan, an honest assessment of fit, and a realistic timeline.
Abdul Mohsin
Steps for completing your project
After purchasing the project, send requirements so Abdul can start the project.
Delivery time starts when Abdul receives requirements from you.
Abdul works on your project following the steps below.
Revisions may occur after the delivery date.
Specification review and system modeling
I review your requirements and derive the system model — the small-signal model for a converter, or the state-space/transfer-function plant for a control system — and confirm the design approach with you before starting.
Topology and control strategy selection
I select the converter topology or control method that fits your specifications, sizing the key components (inductor, capacitor, switching devices) or choosing the controller structure to match your performance targets.