You will get FPGA Design - Run-Time Configurable CNN Computation Modules
Project details
Run-time configurable CNN computation modules provide an alternative solution to implement custom CNN architectures in FPGAs. They can easily be connected to a controller module through 256-bits data interfaces and valid/ready handshake protocol. These modules can be utilized as convolution, pooling and FC layer processors in CNN implementations.
To process required CNN task, convolution filter type, stride step values, input data size and input/output node numbers can be set during run-time for convolution, pooling and FC layer modules. Modules utilize concurrent computation engines that can process up to 1.2 G data/s at 150MHz clock frequency. (data: signed 32-bits fixed point).
For clients who are interested in CNN implementations in FPGAs, these modules will be easy-to-integrate solution.
To process required CNN task, convolution filter type, stride step values, input data size and input/output node numbers can be set during run-time for convolution, pooling and FC layer modules. Modules utilize concurrent computation engines that can process up to 1.2 G data/s at 150MHz clock frequency. (data: signed 32-bits fixed point).
For clients who are interested in CNN implementations in FPGAs, these modules will be easy-to-integrate solution.
AI Development Type
Deep LearningWhat's included
| Service Tiers |
Starter
$1,500
|
Standard
$3,000
|
Advanced
$4,500
|
|---|---|---|---|
| Delivery Time | 30 days | 37 days | 42 days |
Number of Revisions | 1 | 2 | 2 |
AI Model Integration | - | - | - |
Detailed Code Comments | |||
Knowledge Graph | - | - | - |
Model Documentation | |||
Ontology | - | - | - |
Source Code | |||
Taxonomy | - | - | - |
About Cagri
Digital Hardware Design / FPGA Design
Mersin, Turkey - 1:40 am local time
I have a broad range of professional work experience. I worked at a large high-tech company 7 years as a digital hardware design engineer, I worked at a start-up as an electronics design engineer and I also worked as a research associate in research projects at university.
My experience in digital hardware design mainly covers FPGAs and embedded systems. I have hands on experience in FPGA design, embedded board design and schematic/PCB design.
I have developed and implemented CNN accelerators, data decompression algorithms, ML algorithms and signal processing applications in FPGAs. I also designed multi-layer FPGA-based embedded boards that are utilized in complex computation systems.
I have familiarity with Industry Canada (IC) regulations of EMI/EMC requirements and I have work experience in design for manufacturability and design for test (DFM/DFT) processes.
As a freelancer, I provide FPGA design solutions from concept to end-product. Specifically;
- System design, modeling and analysis,
- RTL design with HDL (VHDL/Verilog) or HLS (C/C++),
- Testbench preparation, functional/timing simulations,
- Implementation optimizations (timing, congestion, power),
- Board bring-up and hardware verification.
Steps for completing your project
After purchasing the project, send requirements so Cagri can start the project.
Delivery time starts when Cagri receives requirements from you.
Cagri works on your project following the steps below.
Revisions may occur after the delivery date.
RTL Design
RTL design of the modules. Design elaboration, obtaining RTL netlist. Analyzing and optimizing RTL design.
Functional Simulations
Testbench preparation. Determining test cases. Preparing bus functional models and verification components. Functional verification of the RTL design.